SU1173436A1 - Device for vector forming on the cathode-ray screen - Google Patents

Abstract

A DEVICE FOR FORMING VECTORS ON THE SCREEN OF AN ELECTRON-BEAM PIPE, containing a register, the first block of permanent memory, connected by the first and second outputs, respectively, to the first inputs of the first and second multipliers, connected by the second inputs to each other, and the outputs, respectively, to the first inputs of the first and second summers The first and second digital-to-analog converters, characterized in that, in order to expand the functionality and improve the accuracy of the device, a second block is introduced into it memory, the third and fourth multipliers, the first and second integrators, the first output of the register is connected to the input of the first block of permanent memory, the inputs - to the inputs of the device, the second output through the first digital-to-analog converter - to the second input of the first multiplier, the third output through the second a digital-to-analog converter — with the first inputs of the third and fourth multipliers; the fourth output — with the input of the second fixed memory block connected by the first and second outputs, respectively, to the second with the inputs of the third and fourth of the solid multipliers, ® whose outputs are connected respectively (L with the second inputs of the first and second adders connected by the outputs via the first and second integrators respectively with the corresponding outputs of the device, with

Description

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The invention relates to automation and computing, in particular to information display techniques, and can be used to visually present graphic information on a screen of a cathode ray tube (CRT) in automated control systems, in particular, to solve navigation problems.

The purpose of the invention is to enhance the functionality and increase

device.

The drawing shows a block diagram of the proposed device.

The device contains a register 1, the first 2 and second 3 blocks of permanent memory, the first 4 and second 5 digital-to-analog converters (DAC), the first 6, the second 7, the third 8 and the fourth 9 multipliers, the first 10 and the second 11 adders, the first 12 and second 13 integrators.

The first and second outputs of the first block 2 of the permanent memory are connected respectively to the first inputs of the first 6 and 1 of the second 7 multipliers connected by the second inputs to each other, and the outputs to the first inputs of the first 10 and second 11 adders, respectively.

The first output of register 1 is connected to the input of the first memory block 2, the inputs to the device inputs, the second output via the first DAC 4 to the second input of the first multiplier b, the third output through the second DAC 5 to the first inputs of the third 8 and fourth 9 multipliers, the fourth output - with the input of the second block of 3 permanent memory, connected by the first and second outputs, respectively, with the second inputs of the third 8 and fourth 9 multipliers, the outputs of which are connected respectively to the second inputs of the first 10 and second 11 adders, connected output s 12 through the first and second integrators 13 sootvetstvuyushaya output device.

Register 1 is designed to receive and store the polar coordinates of the vectors to be added.

Blocks 2 and 3 of memory are designed to store codes for the sine and cosine angle table functions and are permanent storage devices (ROM), the contents of each cell of which are equal to the sine or cosine of the address of this cell. Such memory blocks may be made on the basis of consumer-programmable integrated circuits of ROM.

DACs 4 and 5 are designed to convert the modulus vector codes into proportional voltages.

The multipliers 6-9 are designed to digitally multiply the sine and cosine codes of the vector argument by a voltage proportional to the magnitude of the vector, and are four-square multiply digital-to-analog converters.

Adders 10 and 11 are designed to algebraically sum two voltages.

The integrators 12 and 13 are designed to integrate the input voltages during the vectoring time and can be made on the basis of an operational amplifier with a capacitor and an analog switch in the feedback circuit.

The device works as follows.

Register 1 records the code for the polar coordinates of two vectors to be geometrically added (subtracted) on a CRT screen.

The argument codes of the first and second vectors are fed to the inputs of blocks 2 and 3 of the fixed memory, respectively, as a result of which the sine and cosine codes of the first vector are formed at the outputs of block 2 of constant memory, and the outputs of block 3 of constant memory are codes sine and cosine of the second vector argument.

The sine and cosine codes of the argument of the first vector are fed to the digital inputs of multipliers 6 and 7, the analog inputs of which are supplied with a voltage proportional to the modulus of the first vector, converted from the module code using converter 4. As a result, the output of multipliers b and 7 proportional to the projections of the first vector on the coordinate axes X and Y.

The sine and cosine codes of the second vector argument are fed to the digital inputs of multipliers 8 and 9, the analog inputs of which are supplied with voltage from the output of converter 5, which is proportional to the modulus of the second vector, and if the vectors are added, the polarity of the voltage at the output of converter 5 coincides with the polarity of the voltage at the output of the converter 4, if subtraction, then the polarity is opposite. The outputs of multipliers 8 and 9 form voltages proportional to the projections of the second vector on the X and Y axes. Voltages proportional to the projections of vectors along the X axis are summed up by an analog adder 10, and voltages proportional to the projections of vectors along the Y axis, - adder 11. Consequently, at the outputs of adders 10 and I, there are voltages proportional to the projections of the total vector on the X and Y axes. These voltages are integrated by integrators 12 and 13 and fed to the deflecting system of a CRT (not shown), providing a display on the screen CRT vector equal to the geometric sum (difference) of the two input vectors.

Thus, the introduction of the second block 3 of the permanent memory, multipliers 8 and 9, integrators 12 and 13 and their connections allows to expand the functionality of the device and to ensure the possibility of geo 3 1173436d

the metric addition of two vectors, and from the radio location and graphic information of the multiple conversion of the number included in the composition of moving objects,

pulse codes, allows you to increase the true and the accuracy of the device. The strong velocity vectors of moving

The device can be used, in part-g objects, to solve maneuvering tasks.

in mapped and safe discrepancy display systems.

Claims (1)

DEVICE FOR FORMING VECTORS ON THE ELECTRON BEAM TUBE SCREEN, containing a register, a first block of read-only memory connected by the first and second outputs respectively to the first inputs of the first and second multipliers, connected by the second inputs to each other, and the outputs, respectively, to the first inputs of the first and second adders, the first and a second digital-to-analog converters, characterized in that, in order to expand the functionality and improve the accuracy of the device, a second block of read-only memory is introduced into it and, the third and fourth multipliers, the first and second integrators, the first output of the register connected to the input of the first block of read-only memory, the inputs to the inputs of the device, the second output through the first digital-to-analog converter with the second input of the first multiplier, the third output through the second digital-to-analog converter with the first inputs of the third and fourth multipliers, the fourth output is with the input of the second block of read-only memory connected by the first and second outputs corresponding to the second inputs of the third and fourth smart cores, the outputs of which are connected respectively with the second inputs of the first and second adders, connected by the outputs through respectively the first and second integrators with the corresponding outputs of the device. „, 1173436