SU1163271A1 - Correlation-type velocity meter - Google Patents

Abstract

A CORRELATION SPEED METER containing two sensors, two formers, the code of the first of which is connected to the information input of the shift register, two three-input logical multiplication blocks, the inputs of the first of which are connected to the direct, outputs of the second forwarder, shift register and one of the pre-end register cells, and the outputs of the second one with inverse outputs of the second driver, shift register and one of the pre-final cells of the register, the direct output of which is connected to the first logical multiplication unit, the outputs These blocks are connected to the outputs of two OR logic circuits, the outputs of which are connected to the inputs of the integrator connected to the control input of the clock pulse generator whose output is connected to the synchronization inputs of the shift register cells, characterized in that, in order to increase accuracy and reliability, each driver contains a comparator, an integrator and a source of reference voltage, with the output of the comparator connected to the first input of the integrator, the second input of which is connected to the source of the reference voltage, the output and integrator connected to a first input of the comparator, the second input of which is input shaper.

Description

1 The invention relates to a measurement technique and is intended to measure the linear velocity of objects and the path they pass. A device for measuring speed using a correlation method for measuring speed is known. However, this device uses two analog-digital converters and two shift registers, which leads to a complication of equipment. Closest to the invention I is a correlation velocity meter containing two input limiter amplifiers, the output of the first of which is connected to the information input of the shift register, two three-input logical multiplication units, the inputs of the first of which are connected to the direct outputs of the second amplifier-limiter register one of the pre-terminal cells of the register, and the inputs of the second with inverse outputs of the second amplifier limiter, the shift register and one of the pre-terminal cells of the register, direct output to The connection is connected to the first logical multiplication block. The outputs of the logic multiplication units are connected to the inputs of two OR logic elements, the outputs of which are connected to the inputs of the integrator connected to the control input of the clock generator, the output of which is connected to the clock inputs of the shift register cells. The pulse counter is connected to the output of the clock pulse generator C2. However, in a known device with a constant threshold for generating signal signals, the form of the discriminatory characteristic (slope and width of the discriminator aperture) and, accordingly, the accuracy of measuring the object velocity and the probability of tracking failure, which characterizes the reliability of measurement speeds depend on the statistical characteristics of the information signals arriving at the inputs of the limiting amplifiers and A11 leading to a change in the mean value of the signal-signal in their outputs The aim of the invention is to improve the accuracy and reliability of the velocity measurement by generating signal signals with a predetermined average 12 duty cycle, leading to an increase in the steepness and width of the aperture of the discriminatory characteristic. The goal is achieved by the fact that in a correlation velocity meter containing two sensors, two signaling signal generators, the output of the first of which is connected to the information input of the shift register, two three-input logic multiplication blocks, the inputs of the first of which are connected to the direct outputs of the second imaging unit the signal-signals, the shift register and one of the pre-terminal cells of the register, and the inputs of the second - with the inverse outputs of the second signaling signal generator., the shift register and one of the pre-final cells of the reg The source, the direct output of which is connected to the first logic multiplication unit, the outputs of the blocks are connected to the outputs of two OR logic circuits, the outputs of which are connected to the inputs of the integrator connected to the control input of the clock generator, the output of which is connected to the shift register from the clock inputs of the cells, counter the pulses are connected to the output of the clock pulse generator, each driver contains a comparator, an integrator and a source of reference voltage, the output of the comparator being connected to the first input of the integra Ator, the second input of which is connected to a source of reference voltage, the integrator output is connected to the first input of the comparator, the second input of which is input shaper. The drawing shows a functional diagram of the proposed correlation velocity meter. The device contains comparators 1 and 2, voltage dividers R and R integrators 3 and 4, shift register 5, blocks 6 and 7 of logical multiplication, logical elements SHI 8 and 9, integrator 10, controlled (in frequency) generator 11 clock pulses, counter 12 pulses. Each logical multiplication block consists of two logical elements AND 13 and 14, 15 and 16. The device operates as follows. Information signals x (t) and

. 3

xCt + T) with sensors (not shown) with a relative time shift L equal to the transport delay. The signal x (t) is fed to the input of the comparator 1. The reference voltage applied to the comparator sets the level of the signal-signal at its output. From the output of the comparator 1, the signal-signal is fed to the input of the integrator 3, assembled in a differential circuit, to the second input of which a portion of the reference voltage is supplied from the divider R ,, which specifies the required duty cycle of the signal signals.

In integrator 3, the input signals are compared (the average value of the signal with the reference signal). When the mean value of the signal-signal (or duty ratio) changes, a mismatch signal appears, which from the output of integrator 3 is fed to the second input of comparator 1 and changes the threshold of forming the signal-signals until the error signal equals zero, t. e. until the required duty cycle of the signal signals of the output of comparator 1 is established.

Similarly, a given duty cycle is maintained in the second channel, assembled on comparator 2, integrator L and divider Rj.

The signal from the output of the comparator 1 is delayed by the shift register 5 for the time determined by the number of its cells and the frequency of the following clock pulses.

Pulses from the direct outputs of the shift register 5 and the comparator 2 are fed to the inputs of the terminal 13, and pulses from the inverse outputs of the same circuit elements to the inputs of the element 15. When the corresponding pulses coincide in time at the output of the element And 13 and 15, impulse voltages appear. These voltages are fed to the inputs of the element OR 8 from its output — to the first input of the integrator 10.

The inputs of the element 14 are pulsed from the direct outputs of one of the pre-final cells of the 5 shift register and the comparator 2, and the inputs of the element 16 are pulses from the inverse outputs of the same circuit elements. When the corresponding pulses coincide in time at the output of the elements 14

632714

and 16 pulsed voltages occur. These voltages are fed to the inputs of the element OR 9 and from its output to the second input of the integrator 10. 5 The integrator 10 is made according to a differential circuit, i.e. it produces not only averaging of signals from the outputs of elements 8 and 9, but also their subtraction. Using the elements AND 13 and 15, OR (and the integrator 10, as well as the elements AND 14 and 16, OR 9 and the integrator 10, the values of the sign correlation functions are formed, the maxima of which are shifted by the signal passing time between one of the predetermined and last cells of the register five.

In steady state, the difference

The 20 voltages at the inputs of the integrator 10 are zero. If the measured velocity value changes, then the time shift between the input signals changes, and

25, the equilibrium of the follow system is disturbed.

The output of the integrator 10 connected to the control input of the clock pulse generator 11 changes the voltage, which, acting on the generator 11, the output of which is connected to the clock inputs of the register 5 cells, causes a change in the frequency of the clock pulses, and therefore the delay time signal in register 5 until the difference of signals at the inputs of the integrator 8 is equal to zero. At the same time, the frequency of clock pulses is proportional to the magnitude of the measured speed, and the total number of pulses accumulated by the pulse counter 12 is proportional to the path traveled by the object, whose speed 5 is measured.

Compared to the known, the proposed device improves the accuracy of speed measurement by increasing the slope of the discriminative characteristic, increases the reliability of the speed measurement by reducing the probability of tracking failure.

Due to non-linear distortions in the near capacitive path and changes in the law

distribution of the information signal at a constant threshold formatiro. Signum-signal probability of occurrence of the information signal

above or below the set threshold vary. This leads to the fact that the average value of the signal signal is not zero, which degrades the accuracy and reliability of the velocity measurement, and also leads to the dependence of these characteristics on the parameters of the information signal, i.e. to reduce the stability of the meter.

Due to the sensors, the signals x (t) and x (t + LO can differ both in scale multipliers and in shape. Then, with constant thresholds for the formation of signal signals of duration

and the negative values of the signal signals in the direct and delayed channels will be different, which will lead to decorrelation of these signals and increase the speed measurement error.

Thus, adjusting the limiting thresholds in each of the channels so that the average duty cycle of the signal signals is two, increases the stability of the measurement by reducing the effect of non-linear distortions in the receiver.

path, changes in the law of distribution of the information signal and non-identical channels.

mCP}

Claims (1)

A CORRELATION SPEED MEASURER comprising two sensors, two formers, the output of the first of which is connected to the information input of the shift register, two three-input logical multiplication units, the inputs of the first of which are connected to the straight lines - the outputs of the second former, shift register and one of the terminal cells of the register, and the outputs of the second - with the inverse outputs of the second shaper, the shift register and one of the pre-terminal cells of the register, the direct output of which is connected to the first block of logical multiplication, the outputs of these blocks connected to the outputs of two logical circuits OR, the outputs of which are connected to the inputs of an integrator connected to the control input of a clock generator, the output of which is connected to the synchronizing inputs of the cells of the shift register, characterized in that, in order to increase accuracy and reliability, each shaper contains a comparator , an integrator and a reference voltage source, wherein the output of the comparator is connected to the first input of the integrator, the second input of which is connected to a reference voltage source, the output of the integrator n to a first input of the comparator, the second input of which is the input of the former. .. SU „„ 1163271