SU1160573A1 - Receiver of frequency-shift keyed signals - Google Patents

Description

The invention relates to radio engineering, and can be used in communication channels with a multiple ratio of carrier frequencies.

Known receiver frequency-manipulated signals, containing a calculating device, block the formation of the blocking signal, the accumulation unit, the block of discrete measurement of the duration of the intervals between zero crossings [1].

This receiver has increased noise immunity, however, when receiving signals with a multiple frequency ratio, it has an excessive complexity.

The closest in technical essence to the proposed technical solution is a receiver of frequency-manipulated signals containing a series-connected first amplifier delimiter, shift register and phase detector made on the exclusive OR element, a series-connected frequency multiplier, narrowband filter and a second amplifier-limiter, with the multiplier input the frequency is connected to the input of the first amplifier-limiter, the output of the second amplifier-limiter is connected to the clock inputs of the register and the shift [2].

However, the well-known receiver is characterized by low resistance to intersymbol distortion. These distortions arise when transmitting high-speed information over a communication channel with a limited frequency band as a consequence of the influence on the received single element of the response signal of the communication channel to the previous single elements of the signal. This influence leads to such a distortion of the waveform, in which the temporal relations between the positive and negative half-waves of the signal are violated. This is extremely important for a known device, the principle of action of which is based on a comparison of the half-wave signs of two adjacent single signal elements. As a result of intersymbol distortion, the noise immunity of the known device is sharply reduced: with a signal-to-noise ratio of 3-4, the probability of error may increase by two orders of magnitude. The introduction of the intersymbol distortion corrector into the receiver sharply complicates and increases its cost, therefore it is undesirable and not always possible.

The purpose of the invention is to improve the noise immunity.

This goal is achieved by the fact that the receiver frequency-manipulated signals, containing the shift register and connected in series the frequency multiplier, narrowband filter and amplifier limiting, the output of which is connected to the clock input of the shift register, introduced analog-to-digital converter of parallel action, the input of which is the receiver input, combinational subtractor, high-pass filter, the input and output of which are connected respectively to the input of the receiver and the input of the frequency multiplier, amplitude 'de A vector whose input is connected to a narrowband filter output, a digital-to-analog converter connected in series, each input of which is connected to a corresponding output of a combination subtractor and an output comparator, the threshold adjustment input of which is connected to an output of an amplitude detector, N additional shift registers, a clock input of each of which is connected to the output of the limiting amplifier, the input of the shift register and the input of each additional shift register are connected to the corresponding outputs of the analog digital converter parallel action, and the first and second outputs of the shift register and each additional shift register connected to the corresponding inputs of the combinational subtractor.

FIG. 1 shows the structural electrical circuit of the proposed receiver; in fig. 2 - time diagrams explaining his work.

The receiver of frequency-manipulated signals contains analog-to-digital converter 1 of parallel action, register 2 shift, additional registers 3–5 shift, combinational subtractor 6, digital-analog converter 7, comparator 8, high-pass filter 9, frequency multiplier 10, narrow-band filter 11, amplifier limiter 12, amplitude detector 13.

The receiver of the frequency-manipulated signals works as follows.

Consider the work of the receiver for the case number 3.

The input signal (Fig. 2 a) is fed to the input of analog-to-digital converter 1 and is converted into a parallel natural binary code with a sign. Since the receiver operation is illustrated by the example of a receiver with a four-digit analog-to-digital converter 1, the specified code will contain one sign bit (most significant) and three significant digits representing the code of the absolute value of the signal reference. It is accepted to encode the “+” sign as 0, and the “-” sign as 1. Thus, the reference code of the signal 0111 is read as +7, and the code 1101 - as - 5, etc. The code of the analog-to-digital converter 1 is parallel, all its digits appear simultaneously, which is why four registers are used to record them: register 2 and additional registers 3-5. At the time points given by the leading edges of the clocking pulses (Fig. 2 f), v1160573

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the input code of the analog-to-digital converter 1 is written to the specified registers. To read this code at the first outputs of register 2 and additional registers 3–5 (Fig. 2 bd), it is necessary to find in Fig. 2 f the front edge of the clock pulse, which coincides with the required input signal, and fix the contents of the first bits of the registers and additional registers 3-5, counting the signal in FIG. 2 b by the highest digit of the code, and the signal of FIG. 2D - younger. For example, the clock pulse nearest to the origin of FIG. 2 f corresponds to the code 0111.

For further reasoning, we agree to consider the scale such that the amplitude value of the signal in FIG. 2 a will correspond to the code 0110 or 1110 (+ 6 or -6, respectively). If a unit is received, then the half-period of the carrier oscillation of a lower frequency arrives at the input of the analog-digital converter 1, the voltage of which at the reference time will be approximately 0.71 amplitudes. Let it correspond to the code 0101 or 1101 (+ 5 or - 5). Now it is not difficult to establish the correspondence of digital codes (Fig. 2b-e) to the reference values of the input signal (Fig. 2a). It is obvious that the signal reading is taken twice per unit interval.

Further, the code combination recorded in register 2 and additional registers 3–5 is delayed in them. For one period of the clock frequency (a quarter of a unit interval). The delayed code combination is removed from the second outputs of register 2 and additional registers 3-5. Thus, at each clock point in time, at the first outputs of register 2 and additional registers 3-5 there will be the code of the current signal reference, and at the second outputs - the code of the previous signal. Both codes, as mentioned, are four-digit binary numbers. From the outputs of register 2 and additional registers 3–5, these codes are fed to the inputs of the combinational subtractor 6. The number representing the previous counting code is subtracted from the number representing the current counting code, and the subtraction is performed not bitwise, but taking into account loans from the most significant discharge (transfers to the senior level), i.e. according to the rules for subtracting multi-digit binary numbers, i.e. subtract the code formed by the signals of FIG. 2 ek, from the code formed by the signals of FIG. 2 bd with all loans and transfers. The output signal of the combination subtractor 6 (Fig. 2 .l-o) is also a signed natural binary parallel code. It is known that during arithmetic operations the bit depth of the result may increase, therefore

the difference code is reduced to the bitness of the operands (i.e., to four digits) by truncating (discarding) the least significant digit. You can read the difference code in the same way as the codes of the operands (samples), taking into account the comments made about its truncation. In this case, the signal of FIG. 2 l displays the sign bit, and the signals of FIG. 2 MOs are significant digits in decreasing order of seniority. The code difference is fed to the inputs of the digital-to-analog converter 7, where the digital code is converted into voltage (Fig. 2 p). The sign bit of the difference code is not used. The output voltage of the digital-to-analog converter 7 is compared with the threshold level shown in FIG. 2 with a dashed line using the comparator 8. The output signal of the comparator 8 (Fig. 2 p) displays the information embedded in the input signal in a specified way, i.e. the sequence ... 0010100 ... Units in the output signal of the comparator 8 are represented by short pulses, their duration is equal to half of a single interval.

Clock pulses are formed as follows.

The input signal is fed to the filter 9 of the upper frequencies, the cutoff frequency of which is chosen equal to the lower carrier frequency. The signal from the output of the filter 9 of the upper frequencies (Fig. 2) is fed to the input of the frequency multiplier 10, as which, as in the known device, you can use a full-wave rectifier or quad. Narrowband filter 11 extracts the signal of the second harmonic of the larger carrier frequency from the output signal of the frequency multiplier 10 (Fig. 2 t). The output signal of the narrowband filter 11 (Fig. 2 y) is converted from a sinusoidal form to a rectangular amplifier-limiter 12 (Fig. 2 f).

The threshold voltage for the comparator 8 is formed using an amplitude detector 13, which converts the sinusoidal output voltage of the narrow-band filter 11 into a constant (Fig. 2y).

In the absence of intersymbol interference (ICP), the adjacent samples of the specified input signal (FIG. 2 a) taken at clock points of time have approximately the same absolute values and may differ in signs. The alternation of characters is completely determined by the information embedded in the signal. It is on the comparison of these signs that the principle of operation of the known device is based. But with SMEs, a disturbing low-frequency process is superimposed on the signal.

The resulting signal can be viewed as the sum of the desired signal and the SME.

At the same time, signal counts in clock speeds are 1160573.

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cops will differ significantly in absolute values, i.e. some of them will increase significantly, others will decrease to almost zero. Even a slight fluctuation disturbance or impulse disturbance will repeat those readings, the absolute values of which have decreased due to the influence of SMEs. The polarity of these affected samples will be determined incorrectly, which in the known device entails a ₁₀ error. In the proposed receiver, this does not occur, since the absolute value of the difference in neighboring samples is calculated, which is determined by the transmitted information embedded in the received signal and is almost independent of the SME. Indeed, an SME is a relatively low-frequency process, it does not have time to change significantly over the time interval between two adjacent samples (clock interval). Therefore, when subtracting the adjacent samples, the SMEs are almost completely compensated.

Thus, the noise immunity of the proposed receiver is improved compared with the known.

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Claims (2)

A RECEIVER FOR FREQUENCY-MANIPULATED SIGNALS containing a shift register and a frequency multiplier connected in series, a narrow-band filter and an amplifier-limiter whose output is connected to a clock input of the shift register, in which, in order to improve noise immunity, an analog-digital converter of parallel action is introduced into it , whose input is a receiver input, combinational subtractor, high-pass filter, whose input and output are connected respectively to the receiver input and frequency multiplier input, amplitude detector, whose input is connected to the output of a narrow-band filter, connected in series to a digital-to-analog converter, each input of which is connected to the corresponding output combinational subtractor, and the output comparator, the input of the threshold adjustment of which is connected to the output of the amplitude detector, N additional registers The motor, the clock input of each of which is connected to the output of the amplifier-limiter, the input of the shift register and the input of each additional shift register are connected to the corresponding outputs of the analog-to-digital converter of parallel action, and the first and second outputs of the shift register and each additional the shift register is connected to the corresponding inputs of the combination subtractor. Fy 55и_ „„ 1160573 > 1160573 2