SU1160473A1 - Analog storage - Google Patents

Description

The invention relates to computing technology, in particular to storage devices and can be used in systems for collecting and processing information and in object management systems.

Known analog storage. a device containing a storage element on a capacitor, one lining of which is connected to the bus of zero-10 'potential, the first amplifier,

The output of which through the first key is connected to the second capacitor plate and the input of the second amplifier | ~ 1].

.. However, the accuracy and maximum 15 'signal storage time of such a device is small.

It is also known that the analog storage device contains the first amplifier, the output of which is connected to one plate of the storage capacitor, the second amplifier, whose input is connected to the second plate of the storage capacitor and through the first key to its output 25, the second and third keys, which the input of the first amplifier is connected respectively to the input of the device and the output of the second amplifier, which is the output of the device C ³ 3 · 30

The device has a higher accuracy, however, the accuracy and maximum storage time of its signal is small, since the potential change at the device output in storage mode depends on the passage of the output part of the control signal of the first key and on the amount of overload of the storage capacitor by the leakage current of the first key and the input current of the second the amplifier.

The closest to the invention to the technical essence is an analog storage device containing the first accumulative heater <5 ment on a capacitor, the first lining of which is connected to the zero potential bus, the first amplifier, the input of which through the first and second keys is connected / respectively to the 50th input to the output device, the second amplifier, non-inverting input of which is connected to the second plate. the first capacitor and through the third switch with the output of the first amplifier and 55 with one lining of the second capacitor, the fourth switch through which the output of the second amplifier, which is

output device connected to its inverting input and the second plate of the second storage capacitor. The output of this device in the signal storage mode (the first, third and fourth keys are open, the second key is closed) compensates for changes in potential differences between the plates of the first and second storage capacitors caused by passing part of the control signals by the third and fourth keys, the leakage currents of these keys, and also input currents of the second amplifier. As a result, the accuracy of the device in the SPZ storage mode is increased.

However, in the known device mak.simalnoe signal storage time is small since it is limited to the time taken to recharge the capacitor in the first signal storage mode up to the maximum allowable input voltage of the second amplifier _(x2 and leakage current nax

(3 ugpz) third. Key and input current (3β _χ2 ) of the second amplifier

hr · t more

Mox - Crst) Zuts3 ⁺ Zush c1

(ί)

where _Os1 is the initial voltage on the • first capacitor,

available at the time of switching the device to storage mode;

^С 1 '1утС1 - capacitance and leakage current of the first capacitor.

The aim of the invention is to increase the storage time of information device.

. This goal is achieved by the fact that in an analog storage device containing a first amplifier, the input of which is connected to the outputs of the first and second keys, the output of the first amplifier is connected to the signal input of the third key / signal inputs of the first and second keys, respectively , the second amplifier, the output of which is connected to the signal inputs of the second and fourth switches, the first storage element on the first capacitor, one of the plates of which is connected to the output of the first amplification For, another lining of the first capacitor is connected to

- .. 3 1

• output of the fourth key, the second cumulative element at the second con-. A capacitor, one of the plates of which is connected to the zero potential bus, another of the second capacitor 'is connected to the output of the third key, and the control bus, a third amplifier, voltage followers and passive elements are introduced, the first' outputs of which are connected to the output of the third amplifier, the second terminals of the passive elements are connected to the inputs of the corresponding repeaters _; voltages whose outputs are connected to the inputs of the second amplifier, the first input of the third amplifier is connected to the output of the first amplifier, the second input of the third amplifier is connected to the output of the first voltage repeater, the inputs of the voltage followers are connected respectively to the outputs of the third and fourth keys, control inputs of the first, third and fourth keys connected to the lane. control bus, the control input of the second key is connected to the second control bus.

The drawing shows a functional diagram of the proposed device.

The device contains amplifiers 1-3, keys 4-7, accumulative elements on capacitors 8 and 9, repeaters 10 and 11 voltages, passive elements 12 and 13, bus 14 and 15 control and bus 16 of zero potential.

The device works as follows.

In the signal sampling mode, keys 4-7 are closed, and key 5 is open. The capacitor 9 is charged to a voltage and _OC1 equal to

^ οοϊ ^g ( ^and yx ⁺ θ si) A

(2)

where e ₀₁ and A ₅ - respectively nap. 'offset bias

and the gain of the amplifier 1.

The output voltage of the device is

(3)

where A ₂ - gain of the amplifier 2 with open-loop feedback, '

e _og - bias voltage of the amplifier 2.

160473 4

. The capacitor 8 is charged to a voltage equal to

BUT,

BUT,

OS2 ^{: +} ~ _{1 + Dg} ^e 02. (four)

When A,} = 1, this voltage is small. By opening the keys 4, 6 and 7 while simultaneously closing the key 5 y'St10, the device is transferred to the signal storage mode. The capacitor 12 is recharged to the potential difference between its plates; equal to

15

(five)

| Where e ₃ and _e . - bias voltage

amplifier 3 and voltage follower 10, respectively.

20 · Simultaneously with the recharging of the capacitor 8, the recharging of the capacitor 9 occurs. The overcharge currents of these capacitors are

A ₂

25 ........... '"

+

! (6)

thirty

where c | _yykh3 - the voltage at the output of the amplifier 3, '

K _<2 and - resistance resist ditch 12 and 13,

ι З.угт; /,, Пю ", _С 2 - CURRENT UTVCHKI

the keys 6 and 7 of the capacitors U and 8 match, io,

40 ·? 16x2 ^ 26x2 “input currents of amplifier 3,

. With kE = k ₁₃ = kk (υ _{ί6υ χ3} - and _{1s <}

"E _O2 A _< A ₂ / (1 + A., A ₂ ) K, which is easy to do, you can get the same overcharging currents

45 9 and 8, and therefore the same

changes in potential differences between the plates of storage capacitors 9 and 8

50 · 4 C | - L 1> _g (8)

Equal changes in the indicated potential differences caused by the same key management signals 6. And 7 are also taken into account in formula (8).

55 at the time of switching the device to

storage mode. After reaching

potential differences between the plate (capacitor size 8 and _1r2

1160473

discharge of the capacitor prekrascha- _l etsya (3 _g <April ₂ = O), and the current recharge the storage capacitor 9 decreases to

five

7 2 с1 ~ 7ugp 3 * ⁺ 3 с1 ^- с 2 ⁺ ,

θοΐ A ₃ A ₂ (9)

A36H2-—>

ten

where l \ g & _x2 "difference of input currents

amplifier 3. ·

The maximum signal storage time is

15

(and & x2mox - ^ OS1)

I _L p. make = “v

which is more than the maximum storage time of a signal of a known device by the formula (1). The voltage at the output of the device in the signal storage mode is equal to

^{4 and} C2) ^A 7 (11)

^and 1 byyh ' ^(and C1 ^{+ e} 02

• The voltages on capacitors 9 and 8 are equal,

25

'{?one

17 Bh ^{+ e} οι) A. ⁴ Δ ΐ) 1 (12)

thirty

Considering that the voltage at the output of amplifier 1 in storage mode is 35

'^ byk ⁺ ' 04)

we find the voltage at the output of the device;

. , 2 ⁴ Ag. Ar 4 _p ^A 1___1__ ₊

^ Out ⁼ 1+ A ₂ 'O ^ ^a 2 ^Og 1 ⁴ A-ζ 1 ⁺ A ₁ A _g

_e 2 _. ^ + (yy ,, ,, - and _г ) (15)

^e 01 1 <A _g 1 'A, A _g 1 "A _d Ar

The errors of the device with A _< = 1 and 45 A _g »1 are equal

<$ A - -rg ~ ', " ^e <''' ^, A ₂ / & eog - ^e og '^ _g ,

² (16)

50

<^ ai - li, - l and ₂ . _h

Amplifiers 1-3 and voltage followers 10 and 11 are made on integrated-circuit operational amplifiers, for example, on K544UDD2A microcircuits, with amplifier 1 and voltage followers 10 and 11 being switched on with a unit transfer coefficient. Keys 4-7 are made on K59OKN4 microcircuits. As capacitors 8 and 9, capacitors with the same capacitances (C = C 1O ' ^a ) and low leakage currents are used. Resistors 12 and 13 are chosen as resistance values (K | ₂ ~ =

= 10 ⁹ 0m).

As a result of experimental verification of the base object, and the proposed device, it turns out that the maximum storage time of the signal of the proposed device is 6 times longer than the known time.

In addition, with long signal storage times in the proposed device, the average power during sampling decreases by the first and second amplifiers for the charge of the first capacitor, the potential difference between the plates of which is small in the signal storage mode and in the signal sampling mode . With a length of The accuracy of the proposed Device can be higher, because the voltage change on the second capacitor in the signal storage mode in the proposed device is less than the similar voltage change in the known and therefore less error of incomplete suppression of the common-mode voltage by the second amplifier. And with. by changing the voltages on the capacitors in the known device, as compared with the proposed, the voltage drops on the open third and fourth keys increase, which, with an incomplete compensation of their currents, leads to a deterioration in accuracy. ·

1160473

Claims (1)

ANALOG STORAGE DEVICE containing the first amplifier, the input of which is connected to the outputs of the first and second keys, the output of the first amplifier is connected to the signal input of the third key, the signal inputs of the first and second keys are respectively the input and output of the device, the second amplifier, the output of which is connected to the signal the inputs of the second and fourth keys, the first cumulative element on the first capacitor, one of the plates of which is connected to the output of the first amplifier, the other plate of the first capacitor connected with the release of the fourth key, the second storage element on the second capacitor, one of the plates of which is connected to the tire of zero potential, the other facing of the second capacitor is connected to the output of the third key, and the control bus, characterized in that, in order to increase the information storage time it introduced the third amplifier, voltage followers and passive elements, the first terminals of which are connected to the output of the third amplifier, the second terminals of the passive elements are connected to the inputs of the corresponding repetition voltages whose outputs are connected to the inputs of the second amplifier, the first input of the third amplifier is connected to the output of the first amplifier, the second input of the third amplifier is connected to the output of the first voltage follower, the inputs of the voltage followers are connected respectively to the outputs of the third and fourth keys, the control inputs of the first, third and the fourth key is connected to the first control bus, managing (the input of the second key is connected to the second Yashina control. . „Zi., 1160473 > 1 1160473 2