SU1149789A1 - Memory element for permanent storage - Google Patents

Abstract

1. A memory element for a permanent memory device containing a semiconductor substrate of the first type 1 conductor, in the surface layer of which the second-type conduction diffusion regions are located on the surface of the semiconductor substrate and have some edges of the second conductivity type diffusion regions on the semiconductor surface the substrate between the dielectric regions are sequentially placed the first and second dielectric layers with a part by overlapping the other edges of the diffusion regions, a conductive layer is located on the surface of the second dielectric layer, about the same with the fact that, in order to increase the information storage time, the conductive layer is made of two semiconductor layers forming a pn-junction, the thickness of the layer adjacent to the second dielectric layer is less than the diffusion length of carriers, but more than L, equal to where 1 is the mean free path, S is the relative energy transferred by the carrier of oscillation m and the crystal lattice of the semiconductor material layer 1chego wire. 2, A memory element for a permanent storage device containing a semiconductor substrate of the first conductivity type, in the subsurface layer of which diffusion regions of the second conductivity type are located, on the surface of the semiconductor substrate there are dielectric regions with partial overlap of one edge of the diffusion regions of the second conductivity type, on the semiconductor surface the substrates between the dielectric regions are sequentially placed the first and second dielectric layers with With the overlap of the other edges of the diffusion regions, there is a conductive layer on the surface of the second dielectric layer, characterized in that, in order to increase the storage time 4 O, the conductive layer is made of two adjacently arranged semiconductor layers -n-junction, with tolcin layers getting used to the second dielectric layer, less diffusion lengths of carriers, but more than L, equal to where 1 is the mean free path of carriers, and is the relative energy transferred by the charge carrier and the lattice vibrations of the semiconductor material of the conductive layer.

Description

., and

The device is related to computer technology and can be used in the manufacture of memory of Mx devices on oaibse MOS transistors, such as MIOP-type (silicon metal nitride-silicon dioxide).

 the invention is to increase the storage time of the information element g (amti.

i-ia of Fig. 1 illustrates a memory element in accordance with a first embodiment of the invention; In FIG. 2, the same in accordance with the embodiment of the invention.

In the semiconductor substrate I of one type of conductivity (FIG. 1), diffusion regions 2 of a different type of conductivity are detected. On a semiconductor substrate with a partial overlap of one edge of the regions 2 is the dielectric layer 3..

iSa substrate are dielectric layer 4 with overlapping edges of the areas. 5 ana him - Dielectric Globe 5. Both of these image WT zatorny dielectric. "On the gate dielectric there is a conductive electrode of the impurities of the b-semiconductor layers b and 7 g disposed 1-1 of each other and form a {p ^ j transition. The second variant (Fig. 2) differs from the first one in that the semi-proghikovye slMr forming the pn-junction are located adjacent to each other.

Consider the operation of a memory element when a substrate of p-type conductivity is used, the dielectric layer 4 is made of silicon dioxide and thickness tO-SOA, the layer 5 is silicon nitride with tolcine A, the conductive layer is made of silicon, the bottom layer is of p-type conductivity, Upper-type conductivity.

The recording mode is implemented as follows. No where the JD 7mb is applied is a negative polarity voltage of such magnitude as to cause avalanche breakdown in the pn junction. A negative polarity voltage is applied to layer 6 relative to the substrate. This voltage reduces the potential Aurier between the layers & and 5, thereby increasing the accumulation of negative charge in layer 5

Electrons arising in large quantities and with high energy in

9

as a result of lazy breakdown, injection of the waste into layer 6 and being captured by traps.

The erasure is solved as follows. A positive voltage is applied to the layer 7 relative to the substrate. Its value is chosen such that the condition is fulfilled: the current through the layer is much less than the current through layer 5. The applied voltage lowers the potential barrier between layers 6 and 7, the electrons stored in the traps, leave them and

Under the action of the applied voltage, 8 conductive layer 6 goes away. The absence of large currents through layer k makes it possible to avoid a change in its characteristics, which makes it possible to increase trouble-free operation and storage time.

Read mode 8, depending on the sign of the accumulated charge in layer 5 between adjacent regions 2, the channel exists or does not exist. This is determined by the flow (absence) of current between adjacent regions when a voltage is applied between layer 6 and the substrate.

 the layers are followed by

requirements ...

 layer 7 is less diffusion-. carrier lengths, in the MOI4 case, are electrons, since

In the (p) X case, electrons arising in the pn junction region recombine in layer b and do not fall into the –5 layer. This follows from the definition of the diffusion () of the uzion length — the magnitude corresponding to the distance at which the excess carriers. The maximum thickness of layer 6 is determined by the possibility of avalanche multiplication during the breakdown — with a thickness of

layer less than the value of L carriers do not gain energy sufficient for a given multiplication

L

where 1 is the mean free path of the carrier;

6 is relative energy transferred by the charge carrier to oscillations of the crystal lattice of the semiconductor material of the conducting layer. The invention allows to increase the storage time of information, since

wire 1. and the layers consist of two gyplofiber layers, forming a pn junction, which is the source of the charge accumulated in the gate dielectric. In the known structures for accumulating a charge in a gate dielectric, a voltage is applied to the plant and causes its degradation.

ig.1

And 1.2

Claims (1)

where 1 is the mean free path of the carrier; ύ ‘relative energy transferred by the charge carrier to the vibrations of the crystal lattice of the semiconductor material of the conductive layer. The invention allows to increase the storage time of information, since structures for the accumulation of charge in a gate dielectric voltage is applied to the latter and causes its degradation. The II layer consists of two semiconductor layers forming the pn junction, which is the source of charge accumulated in the gate dielectric. R known con