SU1149356A1 - Direct frequency tripler - Google Patents

Abstract

A DIRECT FREQUENCY CLEARER containing a three-phase bridge made on fully controllable switches with an output choke connected, the winding of which has an average tap, forming the first output terminal for connecting the load, a single-core inductive current divider, the winding of which has an intermediate tap, as well as fully controlled keys AC with double-sided conductance to connect two winding inputs to each of the inputs of the said bridge and a control unit including interconnected synchronization node, the network, the master oscillator, the counter-divider by twelve with the outputs of the Hu, 2 .3 A 1 the output of the younger discharge and X4 - the output of the higher discharge, and the decoder, four inputs of which are connected to the counter, and eighteen of it P - P outputs, with triplet switch key inputs, characterized in that, in order to expand the range of output voltage regulation, the second output terminal for connecting the load is formed by one end of the inductive current divider winding, the other end and intermediate water through fully controlled alternating current switches (/) with double-sided conductivity connected to each of the input pins of the said bridge, the decoder being implemented at its outputs the following logical expressions: 4 X t X, -, P, .Pi Xy XC t CO p. - XjXjX j CO XjXjX j PjXjjXjX i P, P Pg x, PsVx, Pt SL Pj x, P, V x, P ,,; P ,. x., P, Vx, Pt o P ,,, VX, PJ, .P ,,,, P, -, P “X, PsVX, P, X, P, Y-X, RH; P „S., P ,, iC, P, P„ x, P, P, .Pj.

Description

one

The invention relates to a converter technique and can be used in triple frequency power supply systems, where improved quality of output and input currents is required.

A valve direct frequency multiplier is known, containing a three-phase controlled valve bridge and a balancing choke, the winding of which has a central tap, the beginning and the end of the winding of the balancing choke are connected to the anode and cathode points of the three-phase valve bridge, the central tap of the winding is connected to one single-phase load terminal, and the other terminal of the load is connected to the zero point of the network. The downstream of this device is that it can work only in three and six types. snom modes. As a result, a sixth harmonic appears in the output current, and the fifth and seventh harmonics in the supply current, which makes smoothing the input and output currents.

The closest to the invention to the technical essence is a valve direct frequency multiplier containing a three-phase controlled valve bridge and a balancing choke, the winding of which has a central outlet, with the beginning and end of the winding of balancing throttle respectively to the anode and cathode points of the three-phase valve bridge, and the winding tap is connected to one single-phase terminal load, and is equipped with 2 two additional three-phase controlled bridges, the inputs E clamps which are connected to the mains, and single-core inductive current divider, the beginning of the winding. which is connected to interconnected cathode and anode points of one additional bridge, the end of the winding is connected to the cathode and anode points of another additional bridge, and another terminal of single-phase load is connected to the tap of the winding of the inductive current divider. The optimal ratio of the number of turns of the winding sections of the current divider is Cos 45: Cos 75 ° 2.73. In this case, the number of turns of the first and second

49356J

the sections are 0.732 and 0.268 respectively. total number of turns of the winding. This difference is ensured by the fact that the valve circuit, the frequency tripler, can operate in 12-pulse mode. As a result, there are no harmonics in the supply current below the 11th, which significantly reduces its distortion, 2.

The disadvantages of the known tripler are the rigid connection between the supply voltage and the maximum output voltage, as well as the limited range of output voltage regulation below the linear supply voltage due to the fact that the single-core current divider performs only the function of providing (j a certain ratio of currents to three phases, and does not serve to match the nominal load voltage with the supply voltage.

The aim of the invention is to expand the range of output voltage control.

The goal is achieved by the fact that in the direct frequency multiplier, which contains the completed

- on fully controlled keys

a three-phase bridge with an output choke turned on, the winding of which has an average tap forming the first output terminal for connecting the load, a single-core inductive current divider whose winding has an intermediate tap as well as fully controllable AC switches with two-sided conductivity for connecting two winding terminals to each of the input pins of the said bridge and the control unit, which include a synchronization node with the network, a generator, and a counter-divider into two orders adtsat with vyho | x rows, Xj, Xs, X ,, where x - output the least significant bit and X4 - yield higher discharge and decoder, which chetfe input coupled to the counter,

 and eighteen of its outputs are Р-P, g with control inputs of triples keys, the second output terminal for connecting the load is formed by one end of the inductive winding

5 current divider, and its other end and intermediate tap through fully controlled AC switches with double-sided conductivity 3

each of the input pins of the said bridge, the decoder being implemented at its outputs the following logical expressions:

g, - XjXjX i Pj XjRjX j

Pj ХХз P P ззХХ;

Fy - XjXjX, r - X2XjX4,

FT X, PjVx, P3V P, X, P, VX, Pt-,

RE x, P, V x.Pji P ,. x ,, P, i

PI, X.P., P ,, j X,, j .P -, P, x.P V Х, РЗ-, Р „x, 1% УХтР4; P „x.P.

P „X, .PS; P X, P ,.

This from; 1 ensures that the electromagnetic coupling between the two winding sections of the current divider is used not only to ensure a certain ratio of currents in the three phases, but also to increase the maximum output voltage relative to the supply voltage. As a result of this, the current divider also performs the function of a step-by-step matching autotransformer, which makes it possible to regulate the output voltage and higher supply voltage and thereby expand the control range.

Fig. 1 shows a printable diagram of the proposed direct frequency multiplier in Fig. 2, a timing diagram of the supply voltage, one phase and load current, as well as a table of the enabled state of the controlled keys; in fig. 3 is a block diagram of a control unit.

The direct frequency multiplier (Fig. 1) contains a three-phase bridge, made on fully controlled keys 1-6, two groups of three fully controllable AC keys with two-sided conductivity, formed from counter-parallel switched on pairs of fully controlled keys 7-8 , 9-10, 11-12 and 13-1А, 15-16, 17-18, respectively, smoothing choke 19 and inductive current divider 20. The beginning 21 and the end 22 of the winding of the smooth throttle 19 are connected to the anode and cathode points of the three-phase bridge, which is filled with fully controllable keys 1–6, and the middle winding outlet 23 forms the first output terminal for connecting the load 24. The single heart connects. l 20 current has a winding with prom93564

a commanding tap 25, one of the two ends 26 and 27 (namely, the end 26) and an intermediate tap 25 through fully controlled keys J 7-8, 9-10, 11-12, 13-14, 15-16 and 17 18 are connected to input terminals 28-30, and the other end of the winding 27 forms a second output terminal for

connect the load 24. Q The control unit (Fig. 3) contains a node 31 synchronization, master oscillator 32, the counter-divider 33 and the decoder 34.

The device works as follows.

At any time: in the on state there are three valves connected to three different input terminals 28-30 and to different valve groups 1-6, 7-12 and 1318. In this case, when in the valve group 13-18, connected to the intermediate tap 25 of the current divider winding, the valve in the polo is turned on. positive direction of the phase currents, then in the valve groups 1-6 and 7-12, the valves are turned in the negative direction of the phase currents and vice versa, and the conditional direction from the power source to the load is taken as the positive direction of the phase currents. As a result, the line voltage between the two phases of the power supply is connected to the winding pins of the current splitter 26 and 25, and the load 24 is connected between the third power supply phase and the current splitter winding terminal 27.

Denote the number of turns and voltage of the winding of the current divider between

0 pins 26, 25 and 27 respectively via Wz € -2S. Zs-it. W.j, and it is Ujr-21, gt. We get

w and

 :."one

2i-Z7 2S-Z5

2b-7

whence it follows that the maximum possible load voltage exceeds the linear supply voltage.

The reduction of higher harmonics in the supply currents d, ig and ip is achieved as a result of the action of the current divider,

The ratio between the instantaneous values of the phase currents required to reduce higher harmonics. For this, the current splitter terminals 26, 25 and 27 are always connected to three different phases, the phase with the highest current being connected to the intermediate tap 25. As a result, the largest phase current is distributed to two components in the other two phases inversely proportional to the number of turns of the sections winding divider current. In order to exclude higher harmonics from the supply current below 11, the ratio of the number of turns of the sections of the winding of the current divider should be equal to Cos 45: Cos 75 °, which corresponds to the number of turns of the sections 0.732 and 0.268 of the total number of turns of the winding of the current divider when valves 2, 11 and 14 are connected to one extreme end 26 of the winding of the current divider, it is connected via valve 11 and clamp 30 to the phase C of the power supply system, the intermediate tap 25 of the winding through valve 14 and clamp 28 to phase A, and the other end 27 to nag ruzku 2A, half of the winding smoothing draw I sat 19, valve 2, and the clamp 29 - with the phase. In the Nebrebrag power supply system, the voltage drops across the switched on valves, in this interval the voltage on the winding zt-is is the linear voltage of the supply voltage, and the voltage of the load branch and is equal to the voltage Ue.2S + 2.-Z И and 15-27 and Taking into account both g.jy VUA 2 (-g and - (i-25 W are obtained for the voltage of the load branch (-U (; A. Taking into account the optimal ratio of the number of turns of the winding sections 0.732: 0.26 "24, , .ti - 0,268: 0,73 voltage of the load branch in this interval is A -0-732 - 0,36bied - I) UCA; UM 2,73 sd, Accordingly, depending on the optimal ratio chosen, the number of turns of sections o the current divider max rolls the instantaneous value of the voltage of the load branch can be 1.23 or 3.34 times the maximum value of the linear voltage of the supply voltage. If the line voltages are sinusoidal, then in the interval in question and the instantaneous voltage of the load branch varies To obtain a 12-pulse operation mode, it is necessary that the voltage of the tripler load branch be formed from identical segments of sinusoids shifted by 30 °. The required shifted sinusoidal half-waves for the formation of the 12-pulse mode can be obtained by selecting the appropriate combinations of switched gates. For example, when the valves 3, 9, and 14 are on, the load branch voltage (ii-ti 1-) 1% is JgA, and this new sinusoid lags behind the sinusoid corresponding to the previous work interval by 30 °, which was required. The sequence of the closure of the valves 1-18, providing a 12-pulse mode of the device (Fig. 1) and thereby triple the frequency of the load current, is shown in FIG. 2. The change in the load current is made by shifting the closure phase of specified valve combinations, and thus also the phases of the supply current relative to the phase of the supply voltage. In this case, regulation is possible both with otrtak cim and with advanced power supply current. The timing diagrams of the supply voltage DC, supply current i, load current i and voltage on the current divider (Fig. 2) correspond to a fully smoothed output current equal to the amplitude /, 60 Id current, and the phase shift between voltage and supply current. The phase shift in all phases is the same, i.e. Yatz f В .Time diagram of the maximum load current (Fig. 2) 1c „corresponds to a phase shift of 4 O. Regulation of the output current from the maximum of others zero corresponds to a change in phase f in the range of 0 ° -90 °. With current fully smoothed in each interval

Loads The shape of the supply current over the entire control range remains unchanged. Accordingly, the spectral composition of the supply current does not change. As a result of the fact that the load current is rigidly connected with the supply current, its shape also does not change, and this current has a rectangular shape and triple frequency.

The control unit, which provides the required algorithm for unlocking fully controlled keys 1-18, operates as follows.

The inputs of the synchronization unit 31 are supplied with the network voltage U and the output voltage x of the highest discharge of the counter-divider 33. At the input of the master oscillator 32, the output voltage of the synchronization unit and the control signal Uy are summed. In the synchronization mode, the voltage frequency of the master oscillator is 12 times higher than the frequency of the mains voltage U and between the output signal x and the voltage, and a phase difference is established that the output signal of the synchronization node compensates for the influence of the control signal U. The counter-divider uses a divider a module of twelve (for example, K155 IE 4), which converts the system Of 12 consecutive time intervals with a duration of 30 eh grades. each in the function x, xj, x ,, x of the binary system (code 1, 2, 4, -6, Table 1).

The states of the P – P, j outputs of the decoder 34 in the HXI time intervals are given in Table 2, compiled on the basis of the closing sequence of pol. 11353568:

by controlled valves 1–18 (Fig. 2, V O).

If you determine the states of pins 1-18, the decoder 34 through the functor when they realize 2

X

four

one

The following logical expressions are

Pj

РЗ

R

X,

X2 xj xj

four

R.-

,: R

23

- XjXj X,

p.

S.Pj VX.P, -,

PC

4 Р

2 3

x.P.Vx.Pj, P, e

 , i p, 11 5c, P, V X, P; P,

R

 x, P ,, ,, x, P, vx, P, i, -, P ". P ,, x, P, Vx, P3i P, x ,, P, i P ,, x, P,,.

The proposed valve direct frequency multiplier expands the control range. This is achieved in that in the wiring circuit the load is connected between the central branch of the winding of a smooth droplet and one extreme terminal of the winding of the current divider, the second extreme step and the intermediate branch of the winding of the current divider are connected to each of the two end windings of the current divider. input pins of the main valve bridge. As a result, the current divider is also used as a matching auto-transformer, which makes it possible to control the output voltage not only lower, but also higher than the supply voltage. Depending on the point of load connection to the winding pins of the current divider, the maximum output voltage can be chosen equal to 1.23 or 3.34 times the linear voltage.

Table 1

1149356

10 Table 2

/ I dC

Ltd

eight

/ J

thirty

1

Queue / Seb mi / rei / / - / (5

and.

I

Uu

31

0 (ere nose / 7 b 6e / 777i // ret / f-fff

FIG. 2

WP,

Jig

Claims (1)

DIRECT FREQUENCY DRIVER, containing a three-phase bridge made on fully controllable keys with an inductor connected at the output, the winding of which has a middle tap, forming the first output terminal for connecting the load, a single-core inductive current divider, the winding of which has an intermediate tap, and also fully controllable alternating current keys with two-sided conductivity for connecting two winding leads to each of the input leads of the said bridge and a control unit including s between a node synchronization · a network "master oscillator, a counter-divider twelve and outputs x _1, x _g, x _3, x _4, where x is ₁ - the output LSB and x ₄ - Principal level output, and the decoder, four inputs of which are connected with the meter, and eighteen of its outputs P ₃ - with control inputs of triples keys, characterized in that, in order to expand the range of regulation of the output voltage, the second output terminal for connecting the load is formed by one end of the winding of the inductive current divider, its other end and in between od through fully managed keys AC with bilateral conductive connected to each of the input terminals of said bridge, and the decoder implements made at their outputs the following logical expression: Pi = P ₂ ^X 2 S ₃ x ₄ i Ρ * · 3 s x ₂ x ₃ x _4> Pi = ^X 2 x ₃ x ₄ i _S = x ₂ x ₃ x ₄ P _t = ^X 2 ^X 3 ^X 4i ₽ = P ₂ Y xA ; p ₈ = χ _ή Ρ ₅ Α / χ., Ρ ₄ i Ρ ₉ =: X, P ₄ VX, ? h " p " = X, Yx R _4, R ₄ ' Pft ^x iPa P _4g x ₁ P ₄ Vx ₁ P _J Ρ ”= ΧιΡ, νΚ, Ρο Ρ ₁₄ = x _n P ₂ vx, P ₃ ; P _1Г = Χ ₁ Ρ ₄ νχ ₁ Ρς ·, P _1t = Jc ₄ P, V χ ₄ ρ, Ρπ = XiWji Ρ _{1 (} = x ₄ P'vS, P ₂ . SU., .. 1149356