SU1149219A1 - Device for checking programs on coordinatograph - Google Patents

Abstract

COORDINATOGRAPH PROGRAMS CONTROL DEVICE, containing the first AND element, connected by an output to the input of an acceleration / deceleration unit, connected by an output to the first interpolator input, characterized in that, in order to improve the speed of the device, a decoder, the first counter, the second counter are entered generator, three second elements And, the third element And, three channels, the order of which consists of a register and four fourth elements And, and the five element And connected by the first input to the output of the generator, the output to the counting the input of the second counter, and the second input to the first outputs of the channel registers connected by the fault inputs to the overflow output of the second counter, the outputs to the first inputs of the corresponding fourth AND elements, the senior data bits to the corresponding coordinate outputs of the interpolator, and the younger information bits - to the outputs of the corresponding second elements And, connected by the first inputs to the information input of the device, the input of the decoder, the first input of the first counter and the first input of the third floor The I input connected to the second input of the interpolator, and the second input to the output of the first counter and the second i inputs of the second I elements connected by the third inputs to the first W outputs of the deymfrator, connected to the input of the First counter, and the output End interpolator interpolator is connected to the first input of the first element AND connected by the second input to the clock input of the device, the outputs of the fourth elements AND of the channels are connected respectively to the coordinate outputs X, Y and Z of the device, and the second inputs dnm bit outputs of the second counter starting and stopping vtody interpolator are respectively connected to the trigger and ostanovochn№1 output device.

Description

This invention relates to automatic control and is intended for use in systems for preparing programs for graphical control of punched tapes to numerical control (CNC) machines. However, due to the difference in the ways in which the input information in the CNC system is specified by the CNC machines, the PA control programs to the CNC machines on the NA require additional input information conversion, which reduces the efficiency of the control. It is known that for CNC systems, machine tools, in particular, those with a stepper drive, for example, a control system of the type H22-1 m, containing an input unit, a conversion unit, an interpolator, a speed setting unit, a stepping drive, and graphic control. Programs can be performed directly connected to him a coordinator. However, due to the inconsistency of the displacements on the CNC machine (4 0.01 mm, L 0.00t mm) and the coordinate system (4 0.1 mm, 4 0.05 m, the drawing speed of the program on the coordinate system decreases. The closest to the invention There is a device for determining the start of braking in a digital program control system consisting of successively connected interpolators, an automatic acceleration and deceleration unit, and an AND 2J element. A disadvantage of the known device is low speed. The goal is achieved by the fact that the decoder, the first counter, the second counter, the oscillator, the second counter, the second counter, the generator, are entered into the device for controlling the programs on the coordinate graph containing the first AND element connected by the output to the input of the acceleration-braking unit connected by the output to the first interpolator input. three second elements And, the third element And, three channels, each of which consists of a register and four fourth elements And, and fifth element And connected by the first input to the generator output, output to the counting input of the second counter a the second input - to the first outputs of the registers of the channels connected to the drop; second inputs to the overflow output | / of the second counter, the outputs to the first inputs of the corresponding fourth AND elements, the senior data bits - to the corresponding coordinate outputs of the interpolator, and the younger information bits to the outputs of the respective second And elements connected by the first inputs to the information input of the device, the input of the decoder, the first input of the first counter and the first input of the third And element connected by the output with the second input of the interpolator, and the second input with the output of the first counter and the second inputs of the second And elements connected by the third, inputs to the first outputs of the decoder connected to the second output of the first counter, and the output of the Interpolator interpolation end connected to the first the input of the first element And connected by the second input to the clock input of the device, the outputs of the fourth elements And channels are connected respectively to the coordinate outputs X,. У and Z devices, and the second inputs to the discharge outputs of the second counter , Starting and stopping interp torus outputs connected respectively to starting and stopping output device. FIG. 1 is a block diagram of the proposed device j in FIG. 2, time diagrams of the operation of the device. The device consists of x 1 switch 1, the first element And 2, block 3 automatic ramping and braking, interpolator 4 and converter 5. Switch 1 contains a decoder 6, the first counter 7, the three second elements And 8-10 and the third element And tt. Converter 5 contains a generator t2, element I, 13, second with counter 14, and three channels (X, Y, Z), each of which consists of a register 15-, 16.17, and even four fourth elements And 18-21, respectively. 22-25 and 26-29, Infrastructure of the input of the device 30, coordinate the outputs of the device (X,), respectively, 31.32 and 33. Inverter 5 is assembled according to the scheme of a binary multiplier. Output . the overflow of the counter 14 is connected to the reset inputs of registers 15-17,

31

The device works in the following way.

Before starting work in the interpolator 4, block 3 of automatic acceleration and deceleration, registers 15-17 are set to zero.

At the same time, the elements And 2,13 and 8-20 are closed. Element 11 is open.

The operation of the device begins with a Start signal, which comes from Interpolator 4 to a photo reader device (not shown). The photo reader reads the frame information from the punched tape line by line and transfers it from the code track outputs to the input of switch 1. Signals from the code tracks in the form of a binary-decimal code (ISO code - 7 bits) go to; the inputs of the decoder 6 and the element And 11. Elements 8, 9, 10 receive signals only from the 1st, 2nd, 3rd and 4th code tracks (information part of the readable line). Simultaneously with the code track sigals, the sync track signals are received at the input of the counter 7, so that when each row of punched tape is read, one is added to the counter 7. Each time a line with an address is read, the item is delimited. 6 generates a signal that zeroes the contents of counter 7 (FIG. 2,). As a result, a binary code of the number of lines read after the address construction is generated in the counter. The information read from the punched tape is passed by the AND 11 element to the input of the interpolator and is not passed by the closed AND elements to the registers 15-17 of the converter 5.

When reading the 7th line after the line with the address (the next tetrad of a number) to the addresses X, Y, Z, 1,, K (in the case of an arc) and X, Y, Z (in the case of a direct), counter 7 generates a signal with a replica of 1 which closes the element 11 and (fig. 2.7-11) and generates a resolution to open the elements of 8-10 (fig. 2, 9,10). As a result, the minor tetrads of displacement along the X, Y, Z coordinates and the initial coordinates The arcs G, J, K are not transmitted to the interpolator (Figs. 2, 11-4). Reception to the interpolator of the remaining addresses of the program frame frame is unchanged, since in them the number of lines following the address is less than seven and counter 7 does not generate a signal ne

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  replenishment. So after

the reception of a frame in interpolator 4 will be set to a straight (arc) section whose dimensions are 10 times smaller than those specified in the program frame (separating the lower tetrad of a number represented by a binary decimal code is equivalent to dividing its value by 10)

At a given interpolation rate, the processing time of the entered frame by the interpolator decreases as a result by 10 times, which is equivalent to increasing its speed by 10 times. In order not to distort the rammers when the working area is drawn by the interpolator, the lower tetrads of displacements along the X, Y, Z coordinates (addresses X, Y, Z) are passed through AND 8.9 or 10 elements to the corresponding converter registers 15-17 5. For this, the decoder 6 at the time of receiving the addresses X, Y, Z overlaps the enabling signals to one of the elements And 8.9 and 10 (Fig. 2.6-8, 6-9, 6-10). As a result, the code of the fallen tetrad (code tracks 1,2,3,4 FSU) of movement along the X coordinate goes to register 15 (. 2, 10-15), the code of the lower tetrad of movement along the Y coordinate goes to register 16 (Fig. 2 , 9-16), and the code of the youngest tetrad of movement along the coordinate Z into register 17 (Fig. 2, v8-17). As soon as one of the registers 15, 16 or 17 receives the code of a number, the element E13 (Fig. 2 15-13, 16-13, 17-13) opens and the input of the counter 14 (phage. 2, 13-14) begins to receive the pulses of the generator 12 (Fig. 2, 12-13). At the same time, the signals from the outputs of those bits of this register, which were set to the logical 1 state when writing to the digital code of the number, open the corresponding elements AND 18-29 (Fig. 2, 15-18, 15-19, 15-20 , 15-21, 16-22, 16-23, 16-24, 16-25, 17-26, 17-27, 17-28, 17-29, the distribution and signals on the diagram is given in the case of writing to the register 15 of the code 7, in the register 16 - code 8, in the register 17 code 9). In the course of the counter 14 operation, the second inputs of the elements 18-29 of its discharge outputs receive pulses whose frequency is proportional to the weight of the discharge (Fig. 2, 14-18, 22, 26, 14-19, 23,27, 14- 20, 24, 28, 14-21,25,29). These outputs through the open elements And 18-29 arrive at the corresponding outputs of the device (Fig. 2, Out. X, Out. In. Out. Z). This process continues until the counter 14 generates an overflow pulse, the counter volume is 16 input pulses (Fig. 2, 14-15, 16.7). In this case, 15 pulses are output from its discharge outputs (8 impulses from the output of the 1st discharge, 4 - from the output of the 2nd discharge, 2nd output of the 3rd discharge, 1 - from the output of 4- th bit) The overflow pulse of the counter 14 produces zero settings in the registers 15-17. As a result, the signals on their outputs disappear, which leads to the closure of the elements 13 and 18-29. The operation of converter 5 is terminated. At the same time, the number of pulses used by converter 5 at any of its outputs is equal to the code value of the number recorded in the corresponding register 15, 16., 17 That number of pulses corresponds to the division balance by ten corresponding movements in the coordinate of switch 1 when entering a frame into the interpolator .

The pulses corresponding to the integer part of the displacements along the X, Y, Z coordinates are generated by the transducer 5 during the operation of the interpolator 4. The interpolator begins its operation from the moment a line with the End of frame (Lf) sign arrives at its input. Interpolator 4 generates a Stop signal to the photo reader and starts processing the entered frame. The speed of testing the entered frame is set by the unit 3 automatic acceleration and deceleration. Initially, the frame processing rate increases from the minimum value to the specified one and, upon reaching this value, remains constant.

As soon as there remains a section equal to the acceleration section at the beginning of the frame, the automatic acceleration and deceleration unit 3 begins to decrease the interpolation speed, bringing it to the end of the frame development to the minimum value. After testing, the next interpolator 4 generates a Start signal to the photo reader. The input of the next frame begins. The described device operation process is repeated. During the operation of the interpolator 4, pulses of a unitary code are sent from its coordinate outputs to the corresponding inputs of the converter. Each interpolator pulse 4 in the corresponding registers 15-17 of the converter 5 records a code of a number equal to ten. Converter 5 converts these codes to the appropriate number of pulses of the unitary code (ten pulses) and outputs them at the corresponding outputs.

Writing in registers 15-17 of converter 5 of an equivalent code equal to ten allows you to restore the true dimensions of the working section, which were reduced 10 times by the switch when the frame was entered into interpolator 4. The frequency of the generator 12 pulses is chosen so that the conversion time The numbers written to K in registers 15–17 of converter 5, were faster than the period of interpolator pulses corresponding to the maximum interpolation velocity. The arising unevenness in the sequence of pulses at the outputs of the device when the interpolation speed changes at the moments of acceleration and deceleration does not interfere with the operation of the stepper motors of the coordinograph, since in the coordinograph the pulses are averaged by scaling unit dividers. The irregularity of the emergence pulses when converting codes of numbers coming from switch 1 also does not lead to malfunctioning of the jog motors, since at this time their speed of rotation is reduced to a minimum.

The proposed device allows, by increasing the interpolation step to a value,. equal to the displacement of the coordinate recorder, increase the speed of drawing programs by 5-10 times as compared with the similar systems. This affects the performance of the hardware used and reduces the time needed to monitor programs.

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Claims (1)

DEVICE FOR CONTROL. PROGRAM ON A COORDINATOGRAPH, containing the first AND element, connected by an output to the input of the acceleration-braking unit, connected by the output to the first input of the interpolator, characterized in that, in order to increase the speed of the device, a decoder, a first counter, a second counter, a generator, three second element AND, third element And, three channels, each of which consists of a register and four fourth AND elements, and a fifth AND element connected by the first input to the output of the generator, the output to the counting input of the second counter, and the second input to the first outputs of the channel registers connected to the inputs to the output of the second counter overflow, the outputs to the first inputs of the corresponding fourth AND elements, the highest information bits to the corresponding coordinate outputs of the interpolator, and the lower information bits to the outputs of the corresponding their second elements And, connected by the first inputs with the information input of the device, the decoder input, the first input of the first counter and the first input of the third element And, connected by the output to the second input of the interpolator, and the second input - with the output of the first counter and second _{about the} inputs of the second elements And, ® connected by third inputs to the first outputs of the de-diffractor connected by the second output to the input of the first counter, and the output End of interpolation of the interpolator * is connected to the first input of the first element AND connected to the second input At the clock input of the device, the outputs of the fourth elements and channels are connected respectively to the coordinate outputs X, Y and Z of the device, and the second inputs to the bit * outputs of the second counter start and stop outputs of the interpolator are connected respectively to the start and stop outputs of the device. > 1,149,219