SU1133590A1 - Interface for linking information transducer with computer - Google Patents

Abstract

1. DEVICE FOR COUPLING. INFORMATION SENSOR WITH ELECTRONIC COMPUTER MACHINE containing the decryption node of the general reset command, the output connected to the reset input of the decryption node of the sample command, the first output of which is connected to the first input of the data synchronization synchronization node, the second output connected by the output of the data output node, connected by the speaker. coordination of the data format, the second output and the first input of which are connected respectively to the first address input of the output information switchboard and the device readiness input, which is different so that, in order to reduce hardware costs, a synchronization node has been entered into it with its own address, a synchronization node of the status bytes, a channel receivers node and a channel transmitters node, the first and second groups of inputs of the channel receivers node are respectively inputs and inputs of the device identification signals, and the first and second groups of outputs are connected respectively to the first and second groups of inputs of the decryption node of the sampling commands, groups of inputs of the block deciphering the common reset command and the synchronous node issuing its own address, the first input of the state byte assignment node and the second inputs of the data format matching node and the data transmission synchronization node are connected to the second group of outputs of the channel acceptance node, the third output of the data format matching node is output device start-up, and the third, fourth and fifth inputs are connected respectively with the first and second outputs and the third input of the synchronization node (LI data transmission, the output of the decryption node to A general reset command, the first input of the synchronization node has its own address and the second input of the synchronization node contains status bytes, the third input of which is connected to the first output of the decryption node of the sampling commands and the first input of the 00 00 decoding node of the general reset command, the second input connected to the Internet output input information commutator and to the second output of the data synchronization node, the fourth input and the second and third outputs of which are connected respectively to the first output and the fourth fifth inputs vschachi sync bytes node condition, the sixth and seventh sootvetstbenno inputs coupled to the first output node and vtorm synchronization issue home address, the group of information inputs of output switch information is an information group WMOs

Description

The device’s address, the second address input is connected to the second output of the state byte synchronization block, and the third output of the synchronization node to generate its own address, and the output group to the first input group of the channel, 1x transmitter, the first and second output groups of which are respectively subscriber information outputs of the device and a group of subscriber outputs of the device identification signals, and the second group of inputs is connected to the first output of the data synchronization node, the third output of the node with nhronizatsii bytes vschachi state, the first output node synchronization vschachi home address and a first and a second output node decryption fetching instructions, a first output of which is connected to the second input synchronization vschachi node home address.

2. The device according to claim 1, characterized in that the synchronization node containing its own address contains two triggers, two impulse drivers, a delay element, an OR element, two NOT elements and two. element I, and the installation input of the first trigger is connected through the first pulse shaper to the output of the first element I, and the reset input to the output of the OR element and the reset input of the second trigger, the input of which is connected via a serially connected delay element and second pulse generator connected to the output of the first trigger, the first inputs of the first and second elements I are connected to the second input of the node, the second input of the first element I is connected to the output of the first element NOT, whose input and the second input of the second element I form group node inputs, the first input of the OR element is first input node, a second input connected to the output of the second AND gate and via a second NOT member to the second output node, outputs of the first and second flip-flops are respectively the third and first output node.

3. A POP device 1, characterized in that the synchronization node of the status byte contains two triggers, two NOT elements, three pulse shapers, three OR elements, a delay element, and three AND elements, the first input of the first OR element being connected through serially connected first the pulse shaper and the element NOT to the sixth input of the node, the second input through the second pulse shaper to the fourth input of the node and the input of the second element NOT, and the output to the installation input of the first trigger, the reset input of which is connected to the input throwing the second trigger, the first output of the node and the output of the second element OR, the first input of which is the second input of the node and the second input connected to the output of the first elevieHTa AND,; the first and second inputs of which are respectively the third and first inputs of the node, the first inputs of the second and the third elements And are respectively the fifth and seventh inputs of the node, the second inputs are connected to the output of the first trigger and the second output of the node, and the outputs respectively to the first and second inputs of the third OR element, the output of which is through the third pulse generator; the delay element is connected to the input v of the second trigger; its output is the third output of the node; the third input of the third element I is connected to the output of the second element HE.

4. Device POP.1, characterized in that the data format matching node contains two triggers, a format switch, a clock pulse generator, a frequency divider, two NOT elements, eight AND elements, four OR elements and two pulse makers, the outputs of the first and The second elements AND are connected respectively to the installation inputs of the first and second triggers, the reset inputs of which are connected to the output of the first OR element, the output of the second OR element is the third output of the node, and the first and second inputs are connected respectively To the outputs of the third and fourth elements I, the first inputs of which are connected to the fourth input of the node, the inputs to the first inputs of the fifth and sixth elements AND | and the first and second outputs of the format switch, whose input is connected to the zero bus of the power supply source, the third input of the third element I is connected to the output of the clock pulse generator and through the frequency divider to the third input of the fourth element I, the second input of the fifth element I is connected to the first input of the node and through the first pulse shaper - with the first input of the third element OR, the second input connected through the second pulse shaper to the forward output of the second trigger, and the output to the second input of the sixth element And, the first and second inputs of the seventh and eighth elements And are connected respectively with the direct and inverse outputs the second trigger, the second inputs with the fourth input of the node, and the outputs form the second; the output of the node, the first and second inputs of the fourth: OR element are connected respectively to the outputs of the fifth and sixth AND elements, and the output is the first output of the node, The first input of the first element AND is the third input of the node, the second input is connected to the second output of the format switch, the first input of the first element OR is connected via the first element NOT to the first input of the node, the second input is the fifth input of the node, the first input of the second element AND connected to the second entrance. node and through the second element is NOT a third; the input of the first element is And, and the second; input - with the release of the first trigger.

one

The invention is open to computer technology and is intended for data input of a computer of the EC series of a computer from non-system external devices - sources of information representing information in binary code.

A device for interfacing external devices with an I / O channel is known, comprising valves, inverters, a receiver, a switch, a start-up and readiness generator, input and output triggers, a counter, and a register I.

The disadvantage of the device is that it requires a large amount of equipment for its implementation.

The closest to the invention in technical essence is a device for interfacing an information sensor with a computer channel, comprising a format receiving and conversion unit, a readiness control unit and a synchronization unit, the first inputs of which are connected to the corresponding information sensor outputs, a subchannel number generation unit , the work end block, the crash block, and the interrogator of the pointers, the first outputs of which are connected to the corresponding inputs of the computer channel, the first inputs of the block Ani query and the query generating unit connected to the second output of the receiving and converting unit

formats, the third output connected to the first input of the block of failures, the second input - to the first output of the synchronization block, the second output of which

connected to the corresponding inputs of the subchannel number forming unit and the finishing unit, the outputs of the computer channel are connected respectively to the inputs of the start blocks

and the completion of the operation, the synchronization unit, the failure unit, and the reception unit and: 2J format conversion.

A disadvantage of the known device is the high cost of the apparatus.

The aim of the invention is to reduce hardware costs. The goal is achieved by the fact that the device containing

the decryption node of the general reset command, the output connected to the reset input of the decryption node of the sample commands, the first output of which is connected to the first input of the transmission synchronization node

data, the second output of the data format node connected to the first output, the second output and the first input of which are connected respectively to the first address input

an information output switch and device readiness input; a sync byte status byte node, a channel receiver node and a channel transmitter node are entered, the first and second groups of inputs of the channel receiver node are respectively groups of channel information inputs and device identification signal inputs, and the first and second groups of outputs are connected respectively to the first and second groups of inputs of the decryption node of the sampling commands, the group of inputs of the decryption block of the common reset command and the Q and C node the first input of the status byte issuing node and the second inputs of the data format matching node and the data transmission synchronization node are connected to the second group of channel receivers node output, the third input of the data format matching node is the sensor start output device, and the third , quarter and fifth inputs are connected respectively to the first and second outputs and to the third input of the data synchronization node, the output of the general reset command decryption node, the first input of the synchronization node issuing a private address and the second input of the state synchronization unit issuing node, the third input of which is connected to the first output of the decryption node of the sampling commands and the first input of the decryption node of the general reset commands, the second input of the information connected to the information input of the output switch and the second output of the node data transfer synchronization, the fourth input and the second and third outputs of which are connected respectively to the first output and the fourth and fifth inputs of the synchronization node of the state byte , the sixth and seventh inputs of the connected 40, respectively, with the first and second outputs of the synchronization node issuing its own address, the group of information inputs of the output information switchboard is the group of informational inputs of the device, the second address input is connected to the second output of the state byte synchronization block and the third the output of the synchronization node issuing its own 50 address, and the group of outputs to the first group of inputs of the node of the channel transmitters, the first and second groups of outputs of which are corresponding Responsible by a group of subscribers, information 55

device outputs and a group of subscriber outputs identification signals

devices and the second group

the inputs are connected to the first output of the data synchronization node, the third output of the synchronization node of the status byte issuing, the first output of the synchronization node issuing its own address and the first and second outputs of the decryption node of the sampling commands, the first output of which is connected to the second input of the synchronization node issuing its own address.

The synchronous node for issuing a private address contains two triggers, two pulse shapers, a delay element, an OR element, two NOT elements and two AND elements, the installation input of the first trigger is connected via the first pulse shaper to the output of the first element AND, and the reset input — to the element output OR and the reset input of the second trigger, the installation of which is connected through a serially connected delay element and the second pulse shaper connected to the output of the first trigger, the first inputs of the first and second elements And soy Ina with the second input of the node, the second input of the first element AND is connected to the output of the first element NOT, the input of which and the second input of the second element AND form the group of inputs of the node, the first input of the element OR is the first input of the node, and the second input is connected to the output of the second element AND and through the second element NOT to the second output of the node, the outputs of the first and second triggers are respectively the third and first outputs of the node.

The sync node of the status byte contains two triggers, two NOT elements, three pulse generators, three OR elements, a delay element, and three AND elements, the first input of the first OR element is connected via serially connected first pulse shaper and the NO element to the sixth input of the node, the second input through the second pulse shaper to the fourth input of the node and the input of the second element is NOT, and the output to the installation input of the first trigger, the reset input of which is connected to the reset INPUT of the second trigger, the first output node and the output of the second OR gate, whose first input is the second input node and a second input connected to the output of the first AND gate, first and second. 511 inputs of which are, respectively, the third and first inputs of the node, the first INPUT1L of the second and third elements AND, respectively, the fifth and seventh inputs of the node, the second inputs are connected to the output of the first trigger and the second output of the node, and the outputs, respectively, with the first and second the inputs of the third element of the scientific research institute, the output of which through the third pulse generator connected in series and the delay element is connected to the installation input of the second trigger, whose output is the third output of the node, the third input of the third element nen with output of the second NOT member. The data format matching node contains two triggers, a format switch, a clock pulse generator, a frequency divider, two NOT elements, eight AND elements, four OR elements and two pulse drivers, the inputs of the first and second AND elements are connected to the installation inputs of the first and second triggers respectively. the reset inputs of which are connected to the output of the first element OR, the output of the second element OR is the third output of the node, and the first and second inputs are connected respectively to the outputs of the third and fourth And elements, the first inputs of which are connected to the fourth input of the node; second inputs, respectively, with the first inputs of the fifth and sixth elements And and the first and second outputs of the format switch, the input of which is connected to the zero bus of the power supply source; the output of the clock pulse generator and through the frequency divider with the third input of the fourth element I, the second input of the fifth element I with the first input of the node and through the first pulse shaper with the first input of the third element SH, the second input through the second pulse shaper to the forward output of the second trigger, and the output to the second input of the sixth element And, the first and second inputs of the seventh and eighth elements And are connected respectively to the direct and inverse outputs of the second trigger, the second inputs - with the fourth input node, and the outputs form the second output of the node, the first and second inputs of the fourth:, element OR are connected respectively to the outputs of the fifth and sixth element; The output is the first output of the node, the first input of the first element is the third input of the node, the second input is connected to the second output of the format switch, the first input is the first element OR through the first element is NOT to the first input of the node, the second input is The first input of the second element I is connected to the second input of the node and through the second element NOT to the third input of the first element I, and the second input to the output of the first trigger. FIG. 1 shows a block diagram of the device, FIGS. 2-8 are functional diagrams of a decryption node of a sampling command, a node of synchronization issuing its own address, a synchronization node of a status byte, a synchronization node of data transmission, a decryption node of a general reset command, a matching node data format, output switch information, respectively, in Fig.9 is a block diagram of the device control algorithm on a computer line. The device (Fig. 1) contains a node 1 of decryption of fetch commands, a node 2 of synchronization issuing its own address, a node 3 of synchronization of issuing status bytes, a node 4 of data transmission synchronization, a node 5 decrypting general reset commands, a node 6 agreeing data format, output switch 7 data, node 8 channel receiver amplifiers, node 9 channel amplifier transmitters, information sensor 1O, device information input 11, device sensor start output bus 12, device readiness input bus 13, subscriber information groups x outputs 14 and subscriber, 3 outputs 15 device identification signals, a group of channel information inputs 16 and channel inputs 17 device identification signals, the first group of outputs 18 and tires 19-25 of the second group of outputs of node 8 of channel amplifiers-receivers, tires 26- 30 of the first group of inputs and the second group of outputs 31 of the node 9 of channel amplifiers-transmitters, a variable format switch 32 of the node 6, bus 33-44 of communications between the device node, bus 45-52 of the group of inputs 18, bus 53-61 of the group of outputs 31 and tires 62-77i

information input 11, bus 78 and 79 outputs of the switch 32.

Node 1 decryption commands sample contains (figure 2) triggers 80 and 81, elements And 82-85, elements HE 86-f, 86 and 87, the element OR 88.

Node sakhronizatsii issue your own address contains (fig.Z) elements And 89 and 90, elements NOT 91 and 92, element OR 93, shapers 94 and 95 pulse, triggers 96 and 97, element 98 delay.

The state byte issue synchronization node 3 contains (FIG. 4) a second trigger 99, a pulse generator 100102, a delay element 103, elements AND 164-106, elements HE 107 and 108, elements OR 109-111, the first trigger 112.

Node 4 of data transmission synchronization contains (figure 5) the second and fourth pulse formers 113-115, elements AND 116-119, triggers 120123, element HE 124, delay element 125, element SHIII 126 and the first pulse 127.

Node 5 decryption commands a common reset contains (6) elements OR 128 and 129, the elements NOT 130 and 131, the elements 132 and 133, the driver 134 of the pulse and the element 135.

The data format matching node 6 contains (FIG. 7) triggers 136 and 137, elements AND 138-145, elements OR 146-149, generators 150 and 151 pulses, a clock generator 152, a frequency divider 153, and elements HE 154 and 155.

The output information switch 7 contains (FIG. 8) the elements OR 156164, the elements AND 165-200, the check bit generator 201 and the bus 202 of the logical unit.

The device works as follows.

The control program of the computer provides a rigid scheme of the procedure of data transmission by the device, including three phases: the initial sampling sequence, the data transmission, the ending sequence.

In the sequence of signals of the initial sampling, the computer channel selects one specific external device from a large number of devices simultaneously (in parallel) physically connected to the channel, transmits to it a command to execute the operation and

receives from it a status byte that indicates whether the device can perform the data transfer operation.

At the signaling level, this procedure is implemented as follows. The channel excites (i.e., establishes a logical unit) bus 19 RAB-K (all subsequent signals make sense only with excited bus 19 PAB-K). The channel places the address of the external device on the information buses 18 (IlttlH-KI BUS-KO) and drives the 20 ADR-K bus. The signals installed on the buses 18 become available to all external devices physically connected to this channel, but logically connects to only one of them whose own address coincides with the address set on buses 18. A device that identifies itself blocks the propagation of the signal on the 21 FBG-K bus and as soon as at the next time the channel excites the FBG-K bus 2 in response to an external device excited and a holding operation until the end of the bus slave 27 And, besides, puts on its output data lines 31 TIRES TIRES-A7-AK's own address and drives the bus 28 ADR-A. I

The channel resets the ADR-K signal.

on bus 20, it checks the address of the connected external device and, if it matches the required one, it places 18 bytes of the command on the information buses, and then drives the UPR-K 25 bus.

In response to the UPR-K, the external device discards the previous information (address and ADR-K) from its output buses, places the initial status byte on them and initiates the UPR-A bus 29.

Having received a status byte, the channel checks it and, if byte in all bits is zero (i.e. the external device is normal, is not busy and can perform the operation), discards the previous one from its tires, informs and initiates the 24 INF-K bus . In response, the external device resets the status byte and the UPR-A signal.

At this point, the initial sampling sequence ends and the data transfer procedure begins.

As soon as the device has generated the first data byte received from the 1Q sensor, having superheated for it a check bit (odd sign), it places it on the buses 31 (SHIN-A7SHIN-AK) and excites the bus 30 INF-A,

The channel removes the INF-K signal from the bus 24, receives the byte, checks the control bit, compares it with the received one and, if a match, re-energizes the 24 INF-K bus. In response, the device removes the INF-A signal from the bus 30, discards the data from the bus 31, and as soon as another byte is formed, puts it on the information bus 31 and again excites the bus 30 INF-A. In the future, all new bytes from the device side are accompanied by an INF-A signal, any time, having received another byte, the channel responds with INF-K.

The program controlling the operation of the device provides an account of transmitted bytes. Considering the last byte, it notifies the channel. The channel, having received the last byte, excites, in response to the INF-A signal, the UPR-K bus 25, which means for the device in this case, an indication to go to the termination procedure.

In the termination sequence procedure, the interface device places the 31 kb of the state byte on the output information buses (the fourth and fifth bits of the byte in the unit, which means successful completion of the work) and initiates the bus

29 UPR-A.

 Channel in response to. The UPR-A signal responds with the INF-K signal and removes the VVR-K signal. The device performs a general reset and disconnects from the channel.

The device is sampled by node 1. The channel excites the signal RAB-K, which is fed to the bus 19 and prepares element 8 for operation (Fig. 2).

 Following this, the channel places on the information buses 18 SHIN-K1 SHIN-KO bytes of the device address (in our case 77 in the binary code 11101110) and excites the bus 20 ADR-K. The device's address code enters the bus 18 and then to the input of the AND 82 element. In this case, the bits of the address code containing the | | zero are inverted by the HE elements 86 At the output of the AND 82 element, a unit is set that permits operation

element E 83. At the moment when the channel excites the bus 20, a high level signal arrives at the ele; And 83 sets the trigger 80 to one state. With the direct output, the trigger 80 allows the element 84 to work, and the inverse output prohibits the operation of the element 85, thereby blocking the propagation circuit of the VBR-K signal to other external devices.

At the next time point, the channel excites the VBR-K sampling signal, which enters the bus 21 and further to the inputs of the And 84 and 85 elements. Since the operation of the And 85 element is prohibited by the inverse output of the trigger 80, the VBR-K signal does not propagate further. Only the AND 84 element operates and sets the trigger 81 to the single state. In this case, the inverter output 81 prevents the operation of the AND 85 element, and the direct output excites the bus 27 (RAB-A signal). The signal RAB-A allows the operation of nodes 2-5 of the device and through the channel transmitters of node 9 enters the computer channel. The channel on the signal RAB-A removes the signal ADR-K from the bus 20. In this case, the logical zero established on the bus 20 is inverted by the NOT 87 and the trigger 88 resets the trigger 80 via the OR 88 element. In this case, the trigger 81 remains in the 1st state unit until the data transfer procedure is completed. Logical zero, established after channel reset of the ADR-K signal on pin 20, enters node 2 (Fig. 3). The ADR-K signal inverted on the HE 91 element allows the operation of the And 89 element, to which a high level signal is applied to the other bus 27 RAB-A. As a result, shaper 94 is started, which sets to units-. The trigger state 97. The high level signal from output 35 enters the input of output switch 7, ensuring that the information buses contain 31 bytes of the device’s own address.

The same signal triggers shaper 95. A short pulse generated by it is delayed by delay element 98, and then a trigger 96 is set to one state, the direct output of which excites pi NU 28 ADR-A, informing the channel that 31 is 111 dits bytes of the device’s own address. The delay of the pulse from the output of the generator 95 is necessary in order to prevent the generation of the control bit of the byte of the own address by the driver 201 and send it to your 61 SIN-AK before the ADR-A signal on the bus 28 is excited. By the ADR-A signal accepts an address byte, checks whether the received address matches the address of the required device, and, if successful, checks the information buses with 18 bytes of the command, after. What excites the signal UPR-K. Due to the fact that this device is intended only for transmitting data to the computer from an external non-generic information sensor, such as a microphone for voice input, there is no need to decipher the command byte and generate appropriate control signals to ensure its execution. If, in response to the ADPA-A signal, the channel responds with an UPR-K signal, then in this case it is an indication to the device to indicate whether it is capable of performing the transfer operation. data and, if yes, then start the transfer. The UPR-K signal enters the node 25 at node 2 at the input of the element AND 90. Since its other input is affected by a high logic level of the RAB-A signal from bus 27, a unit flashing at the output of element 90 90 drops through the element IL 93 triggers 97 and 96. As a result, the information address 31 removes the byte of its own address and the ADR-A signal from the bus 28. The signal from the input of the element And 93 is inverted on the element HE 92 and is fed through the outputs 31 to the first input of the element 106 and prohibits its operation (figure 4). At that moment, when as a result of resetting the trigger condition 97 and 96, the ADPA-A signal was removed, the driver 100 is started via bus 28 through the NOT element 107 and the trigger 112 is set to one through the OR element 109. a high level from its output through the bus 38 enters the input of the output switch 7 and provides to the bus 31 the initial state byte. In addition, the signal from the output of the trigger 112 is fed to the second input of the element AND 106, at 0 the third input of which is fed through the bus 36 by the element NOT 108 inverted by the element 108 from the direct output of the trigger 123, which is in the initial state (Fig.5). After resetting the ADPA-A signal on the bus 28, the channel removes the UPR-K signal on the bus 25, as a result of which a high potential is established on the bus 34. Element AND 106 is triggered and through element OR 111 starts shaper 102. A short pulse from the drive of shaper 102 is delayed by delay element 103, after which sets trigger one 99 to one state. As a result, the TPR-A signal, which notifies the channel that the initial state byte is placed on the information buses 31. The channel checks it and, if all the byte bits contain zeros, it raises the INF-K signal on the bus 24. The INF-K signal enters the input of the AND 104 element (figure 4). At the first input of the element AND 104, the bus 27 receives the signal RAB-A, which is held until the end of the data transfer. Element AND 104 is triggered and, via element OR 110, it resets triggers 112 and 99, after which the NPR-A signal and the initial state byte are removed from buses 28 and 31. At the same time, the signal from the input of the RSHI element 110 is fed to the bus 37 to the input of the element OR 126 (FIG. 5), which starts the driver 113. The pulse from the output of the driver 113 performs a preliminary reset of the trigger 120 and 122 controlling the data transfer, and through the element 124 prohibits the operation of the element 117, This precaution prevents the trigger 120 from being accidentally triggered at the moment when transients occur in it associated with its resetting. At the same time, the impulse from the output of the for-O detector 113 sets the trigger 121 (recall INF-k) to a single state, the output of which is connected to the input of the element AND 116, further dispersed by its operation, and also to the bus 41. The potential of high level from the bus 41 enters the input of evil 6. According to the purpose of the node 6, agreeing the format of the data. Data is exchanged between the information sensor 10 and the device, for example, in the start-stop mode. The device excites the Start signal on the bus 12, according to which the sensor 10 forms a quantum dannk. During the formation period, the device is in standby mode (stop mm). After the sensor 10 has generated a quantum of information in its output register (not shown), it activates on the bus 13 a Ready signal that activates the device to read the requested quantum of information. At the next moment, the device again excites the Start signal, etc. In the event that the output sensor register size of the sensor does not exceed the data transmission channel size, each request cycle from the device side takes one quantum of data quantum generation. However, if the width of the output register of the sensor is higher (for example, 2 times) of the transmission channel size, it becomes necessary to organize two cycles of data transmission, i.e. reconcile data formats. The proposed device provides the ability to work in single-byte and two-byte modes by setting the switch 32 (Fig.7). The position of the switch 32 shown in FIG. 7 corresponds to a single byte mode of operation. So, the high level potential from the bus 41 enters the outputs of the elements 140 and 141, allowing them to work. However, the second input of the element 14 through the bus 77 from the switch 32 is given a zero potential prohibiting its operation, while the second input of the element And 140 through the bus 76 is given the potential equivalent to a high level. Since the third input of the And 140 element is connected to the output of the racine generator 152, the clock frequency pulses go through the IPI element 147 to the signal bus 12 Starting the information sensor 10. After some time after the arrival of the first pulse, the sensor 10 places on its output register a byte of information and excites the Ready signal, which is fed through bus 13 to the second input of the AND 142 circuit. Since 113 the first input of the AND 142 element is fed through bus 76, the potential equivalent to a high level, the element AND 142 is triggered, and the signal from its output through the element OR 149 and the bus 40 starts the driver 127 (figure 5). A short pulse from the output of shaper 127 is fed to the input of element 117, on the other inputs of which high potentials are applied, (the RAB-A signal on bus 27 is held until the end of the data transfer, trigger 121 is set to one, allows operation of element 116 one input triggers the zero state, the unit at its inverse output allows the element I 116 to work through the other input, the potential of the low level is kept at the output of the generator 113, which through the element HE 124 also allows the operation of the element 117 117). The impulse from the output of the element 117 sets the trigger 120 to one state. As a result, the potential of the high level goes to iny 42 and dapee to the second inputs of the elements 145 and 144 (Fig.7). Since, when operating in the single-byte transfer mode, the trigger 137 is in the initial, reset state, the potential of the high level at its inverse output permits the operation of the AND 145 element. A single signal from the output of the latter goes through the bus 44 to the address input you-; an output switch 7, which provides data transmission from the output register of sensor 10 to buses 31. At the same time, the high potential at the output of trigger 120 starts the driver 114. A short pulse from the output of the 1J14 driver is delayed by the element 125 / delayed, and then the trigger is set to one 122. The potential of the high level at its direct output excites in bus 30 an INF-A signal, which notifies the channel that the data byte is ready and is on buses 31. The channel removes the signal INF from the bus 24, reads the data byte , completes the check bit and, if it coincides with the check bit, by the high-voltage channel, again raises the INF-K signal on bus 24, requiring the transfer of the next byte. Thereafter, the procedure for transmitting each byte of data is repeated in the same manner as indicated. At that moment, when the channel will read the last data byte provided by the control program, the channel in response to the INF-A signal excites on bus 25 a UPR-K signal, which goes to the input of the And 118 element (figure 5). Since the trigger 121 (Hall of the INF-K thread is in the single state and allows operation of the element 118, the high level from its output is triggered by the shaper 115, which sets the trigger 123 (state byte) to the distance. high level from its direct output goes through bus 36 to the output commutator. 7, preparing it for the final state byte. Simultaneously, the high level potential from the single output of the trigger 123 enters the input of the OR element 12 and starts the driver 113. The impulse from the output formir The trigger 113 resets the data transfer triggers 120 and 122. This trigger has no effect on the state of trigger 121 (Remember INF-K), since it is set to one state. Since trigger 123 is set to one state, and the trigger 122 is reset to its original state, this ensures the operation of the element 119, the high potential from whose output via the bus 39 prepares the element 105 for operation (figure 4). In addition, the potential of a high level of a single trigger output 123 via bus 36 starts the shaper 101, which through the element OR 105 sets the trigger 112 to a unit. The potential of a high level from its output goes through the bus 38. To the output of the output switch 7, providing a byte terminal nor to the information busses 31. At the same time, the potential of the high level from the output of the trigger 112 through the element AND 105 and the element OR 111 starts the driver 102. A short pulse from the output of the driver 102 is delayed by the delay element 103 then establishes a single flip-flop 99. The state, is excited on the bus 29, the signal UPR-channel A receives ,, koiechny byte state and in response to CPD-A turned on bus 24, IFN-K signal. The INF-K signal is supplied via the AND bus 135 of the element (Fig. 6), the potential of the output level from the output of which, through the OR 129 element, drives the generator 134 to reset all the device nodes to disconnect the device from the computer channel. A general reset of the device may also be initiated by the channel in cases when an incorrect situation occurs at some phase of its operation, for example, a check bits of an address byte or data byte is detected. In such cases, the channel can set a BLK-K signal and simultaneously capture a RAB-K signal (buses 22 and 19). In another case, the channel removes the FBG-K signal and sets the ADP-K signal when a RAB-A signal is present (buses 27, 20 and 21). In addition to these cases, a general reset can be made by the operator after turning on the power of the device to bring it back to its initial state of readiness by pressing the Reset button, ensuring that the high level potential is applied to the bus 23 of node 5. Starting switch 7 provides data to various output information 31 , namely, the byte of the own address, the initial byte, namely, the byte of the own address, the byte of the initial state, the bytes coming from the information sensor 10, and Ait audio finite state. For each transmitted byte, shaper 201 generates a check bit, which is assigned to the SIN-AK bus 61. The inputs of the elements And 165-200 are conventionally divided into signal and information. All signings are grouped into four groups gated by the respective control bus in the following way. Bus 35 allows the transfer to the bus 31 bytes of its own address. The byte code of the own address (in this case, 77, and in the binary representation 11101110) is constantly sewn on the information inputs of the AND elements 165, 169, 173, 181, 185, 189 and 206. All the information inputs (information inputs) of these And elements contain unit, connected to bus 202 to which a potential equivalent to a logical unit is continuously supplied. Inputs i of two bits containing zero are connected to ground (elements And 177 and 206).

Bus 38 permits the transfer of 31 bytes of the initial state to the buses. Byte code, except for two bits - four. The one and the fifth (And elements 178 and 174) connected to the bus 36 are also permanently sewn up on the information inputs of the And elements 166 ,. 170, 182, 186, 190 and 194, for which the potential of the land is applied. Two bits, connected by bus 36, are connected to the single output of trigger 123. (Status Byte) of node 4 (Fig. 5). At the phase of the initial byte of state, trigger 123 is cleared, which ensures a reference to the 4th and 5th bits of the byte, which is logical. On the phase of the final byte of the state, the trigger 123 is inserted, which ensures that the quarter-fifth and fifth-byte bits are sent, which is indicated by the channel Finished, the slave ended. Bus 43 and 44 allow data to be transferred to bus 31. When operating in single-byte transfer mode, only bus 44 is activated, connected to the output of data format matching node 6 (FIG. 7), thereby allowing data transmission from the output (single-byte) register of sensor 10 (FIG. 6) to inputs 62, 64, 66, 68, 70, 72, 74 and 76. When operating in double-byte mode in the direct data transfer procedure, the node alternately activates buses 43 and 44, providing transmission to tires 31 first the highest byte of data found on even input buses 62-76, and then the youngest its byte coming from the corresponding portion of the output register of the sensor 10 on lines 63, 65, 67, 69, 71, 73, 75 and 77. By setting switch 32 to the vertex position hnee scheme is carried out in a two-byte transfer device. data transfer mode. At the same time, the potential 76 of the node 140 is applied to the bus 76 of the node. Therefore, the data transmission resolution signal sent to the bus 55 41 only activates the element 141. The second input of the element 1.41 receives the generator 152 pulses following which is halved by a divider 153.

The halving of the clock frequency in double-byte data transfer mode is due to the following circumstances. In those cases when the duration of the procedure of one data generation cycle by sensor 10 is less than 2Т, where T is the time of one data transfer cycle from the device to the computer's glow, a two-byte transmission mode causes an overflow situation in the output register of the sensor 10, since in one data generation cycle the device must perform two data transfer cycles, as indicated before. Thus, from the output of the element AND 141, the clock pulses arrive at the element OR 147 and further to the output bus 12, having started the information sensor 10. After the sensor 10 generates a quantum of data, it excites the Ready signal on bus 13 arriving at the input of the imaging unit 130. At the same time, this signal enters the input of the AND 142 element blocked by the switch 32. The current impulse from the output of the imaging 150 arrives through the element OR 148 to the input of the element AND 143, an open potential with the switch 32. As a result, a unit is established at the output of the element AND 143, which through the element OR 149 and the bus 40 provides the generation of a signal. Place the data on the output bus Erez unit 4 to the bus 66 and further to the second inputs of AND gates 144 and 145J takkak But by this time flip-flop 137 is in the initial state and at its inverted output is held unit, it is allowed to work only AND gate 145. As a result, the potential high. This level goes to the bus 44 4j yes-. Further, the output switch enters the transmission of the high byte to the computer channel, which is accompanied by an INF-A signal on bus 30. In response to an INF-A signal, the channel removes an INF-K signal from bus 24, receives a byte and checks its check bit The signal from the bus 30 INF-A is fed to the first input of the element And 138. The potential of the logical

units with a switch 32, and the third input is an INF-K signal that is inverted on the HE element 155 of the bus 24. Since at the moment the channel is cleared by INF-K, a unit 13 is set at the output of the NOT 155 element. As a result, the trigger 136 is set to one, preparing the AND 139 element for operation.

After the channel checks the check bit and the test result is successful, it again raises the INF-K signal on bus 24, indicating the need to transfer the next data byte.

Now the potential of the high level INF-K from the bus 24 goes to the first input of the AND 139 circuit, and since it is already prepared for operation by the trigger 136 on the second input, the unit setting the output of the circuit enters the trigger 137 in one state.

This provides for re-switching the elements of AND 145 and 144, thereby creating the conditions for transmitting the low byte, and starting the driver 151. A short pulse from its output goes through the elements of UTI 148, AND 143 .and OR 149 to bus 40, initiating the next transmission cycle data, this time - low byte. After checking the check bit byte

The channel will again trigger the INF-K signal, but it will not be able to initiate the next data transfer clock in the device, the trigger 137 will be held in one state, and the shaper 151 will start by switching the potential from low to high. Therefore, the device remains in standby mode until the next pulse arrives on the bus 12 from the generator 152. This pulse triggers the sensor, which, for the time it needs to form a data quantum, will remove the Ready signal from the bus 13. As a result, the low-level potential inverted on the HE element 154, through the OR element 146, resets the flip-flops 136 and 137. Thus, the data format matching node 6 is returned to the initial readiness state, and the subsequent data transfer procedure is repeated is.

Thus, the proposed device with. less comparing to the known hardware costs, it provides the interface of a computer with various information sensors, such as analog-digital converters, measuring instruments, process recorders, etc.

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Claims (4)

1. A DEVICE FOR PAIRING AN INFORMATION SENSOR WITH AN ELECTRONIC COMPUTER MACHINE, comprising a decryption unit for a general reset instruction ₍ output connected to a reset input of a decryption unit for sampling instructions, the first output of which is connected to the first input of the data transmission synchronization unit, the second output connected to the first output of the matching unit data format, the second output and the first input of which are connected respectively with the first address input of the output information switch and the readiness input of the device, characterized in that then, in order to reduce hardware costs, it introduced a synchronization node for a private address, a synchronization node for a status byte, a channel receiver node and a channel transmitter node, the first and second groups of channel receiver node inputs being groups of channel information inputs and signal inputs, respectively device identification, and the first and second 'groups of outputs are connected respectively to the first and second groups of inputs of the decryption node of the sampling commands, the groups of inputs of the decryption block to the mand of the general reset and the synchronization node issuing its own address, the first input of the state bytes issuing node and the second inputs of the data format matching node and the data synchronization node are connected to the second group of outputs of the channel receiver node, the third output of the data format matching node is the start sensor output of the device, and the third, fourth and fifth inputs are connected respectively with the first and second outputs, § and with the third input of the data synchronization unit, the output of the decryption unit of the general reset commands, the first m is the input of the synchronization node of the host address and the second input of the synchronization node of the status bytes, the third input of which is connected to the first output of the decryption node of the sample commands and the first input of the decryption node of the general * reset commands, the second input of the information switch output connected to the information input and to the second output of the data synchronization unit, the fourth input and the second and third outputs of which are connected respectively to the first output and the fourth and fifth inputs of the synchronization unit and status bytes, the sixth and seventh inputs connected respectively to the first and second outputs of the synchronization node of the home address, the group of information inputs of the output information switch is a group of information inputs of the device, the second address input is connected to the second output of the synchronization block issuing status bytes, and the third the output of the synchronization node issuing its own address, and the group of outputs is to the first group of inputs of the channel transmitter node, the first and second groups of outputs of which are respectively, by the group of subscriber information outputs of the device and the group of subscriber outputs of the identification signals of the device, and the second group of inputs is connected to the first output of the data synchronization node, the third output of the status byte synchronization node, the first output of the own address address synchronization node, and the first and second outputs of the decryption node sampling instructions, the first output of which is connected to the second input of the synchronization node for issuing its own address. 2. The device according to claim 1, characterized in that the synchronization node issuing its own address contains two triggers, two pulse shapers, a delay element, an OR element, two NOT elements and two AND elements, the installation input of the first trigger connected through the first pulse shaper to the output of the first AND element, and the reset input to the output of the OR element and the reset input of the second trigger, the installation input of which is connected through a series of delay element and a second pulse shaper to the output of the first trigger, the first inputs s of the first and second elements AND are connected to the second input of the node, the second input of the first element AND is connected to the output of the first element NOT, the input of which and the second input of the second element AND form a group of inputs of the node, the first input of the OR element is the first input of the node, and the second, the input connected to the output of the second element AND and through the second element NOT to the 'second output of the node, the outputs of the first and second triggers are the third and first outputs of the node, 3. A device according to claim 1, characterized ^- in that the synchronization bytes dispensing assembly comprises a two state latch, two NOT element, three pulse shaper, three element. OR, delay element and three AND elements, the first input of the first OR element connected via series-connected first pulse shaper and the element NOT to the sixth input of the node, the second input through the second pulse shaper k. the fourth input of the node and the input of the second element is NOT, and the output is to the installation input of the first trigger, the reset input of which is connected to the reset input of the second trigger, the first output of the node and the output of the second OR element, the first input of which is the second input of the node, and the second input is connected to the output of the first element And; the first and second inputs of which are the third and first inputs of the node, the first inputs of the second and third elements of And are the fifth and seventh inputs of the node, the second inputs are connected to the output of the first trigger EPA and a second output node, and respectively outputs the first and second inputs of a third OR gate, whose output via a series ETS; third union of pulse shaper and delay element is connected to. the installation input of the second trigger, the output of which is the third output of the node, the third input of the third element AND is connected to the output of the second element NOT. 4. The device according to claim 1, characterized in that the data format matching unit contains two triggers, a format switch, a clock, a frequency divider, two NOT elements, eight AND elements, four OR elements and two pulse shapers, the outputs being the first and second elements AND are connected respectively to the installation inputs of the first and second triggers, the reset inputs of which are connected to the output of the first OR element, the output of the second OR element is the third output of the node, and the first and second inputs are connected respectively to the outputs of the third and fourth elements AND, the first inputs of which are connected to the fourth input of the node, the second inputs are respectively the first inputs of the fifth and sixth elements AND | and the first and second outputs of the format switch,!, the input of which is connected to the zero bus of the power supply niya, the third input of the third element And is connected to the output of the clock pulse generator and through the frequency divider to the third input of the fourth element And, the second input of the fifth element And is connected to the first input of the node and through the first pulse former the input of the third OR element, the second input connected through the second pulse former to the direct output of the second trigger, and the output to the second input of the sixth element And, the first and second inputs of the seventh and eighth elements And are connected respectively to the direct and inverse outputs of the second trigger, the second inputs - with the fourth node input, and the outputs form the second node output, the first and second inputs of the fourth OR element are connected respectively to the outputs of the fifth and sixth AND elements, and the output is the first node output, the first input q of the first AND element is the third input of the node, the second input is connected to the second output of the format switch, the first input of the first OR element is connected via the first element NOT to the first input of the node, the second input is the fifth input of the node, the first input of the second AND element is connected to the second input. node and through the second element NOT with a third—; by the input of the first element And, and the second input, with the output of the first trigger.