SU1116522A1 - Frequency multiplier - Google Patents

Abstract

A MULTIER OF FREQUENCY, containing two semiconductor diodes, one of the same electrodes of which are connected to the corresponding terminals of the secondary winding of the input transformer, the midpoint of which is connected to one output of the load, about T and that, in order to increase efficiency, two transistors are inserted into it, two additional secondary windings of the input transformer and two capacitors, each capacitor being connected between the other output of one of the semiconductor diodes and the second output of the load, will complement flax secondary winding of the input transformers pa is connected between the base and emitter of one of transistors, a collector and an emitter of each transistor connected to the corresponding one of the electrodes heteronymic semiconductor diodes ...

Description

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0in.1 The invention relates to radio engineering and can be used as a source of harmonic oscillations, in particular in communication systems. Known frequency multiplier for two-pole with nonlinear current-voltage characteristics tl. However, when a frequency is multiplied by a factor of two, its maximum efficiency does not exceed 25%, because most of the power drawn from the signal source is converted to the power of the constant component. The closest to the proposed is a frequency multiplier containing two semiconductor diodes, one of the same electrodes of which are connected to the corresponding secondary terminals of the input transformer, the midpoint of which is connected to the load terminal, while the cathodes of the semiconductor diodes are connected to another load terminal t 23. However, the efficiency This frequency multiplier is also relatively low, since semiconductor diodes convert most of the power supplied to them into constant power. soup The purpose of the invention is to increase the efficiency. To achieve the goal, a frequency multiplier containing two semiconductor diodes, one of which of the same name are connected to the corresponding terminals of the secondary winding of the input transformer, the midpoint of which is connected to the load terminal, two transistors are inserted, two additional secondary windings of the input transformer and two capacitors; each capacitor is connected between the other output of one of the semiconductor diodes and the second load output each ichna the transformer input winding is connected between the base and .emitterom one of the transistors and the collector and emitter of each transistor connected to the corresponding electrodes heteronymic one of the semiconductor diodes. Figure 1 presents the circuit diagram of the pre-frequency frequency multiplier; figure 2 timing diagrams of his work. The frequency multiplier contains an input transformer 1 with a secondary winding 2 and additional secondary windings 3 and 4, semiconductor diodes 5 and 6, transistors 7 and 8, con-, capacitors 9 and 10, and load 11. The frequency multiplier works as follows. When a sinusoidal voltage input is applied to the primary winding 12 of the input transformer 1 with frequency (bi on its secondary winding 2 and additional secondary windings 3 and 4, the voltage is applied with the same frequency. Since the voltage on the top (in Fig. 1) half of the secondary winding 2 of the input transformer 1 and the additional winding 3 have a phase shift with respect to the voltage on the lower half of the secondary winding 2 of the input transformer I and the additional winding 4, then the processes in both arms of the push-pull circuit containing the same the elements are identical and flow with a half-period shift, therefore the processes occurring in the frequency multiplier are considered in one half of the push-pull circuit under the assumption that the load resistance is zero. The additional secondary windings 3 and 4 of the input transformer are intended for switching transistors 7 and 8. With a positive voltage half-wave (Fig. 2a is a continuous line) on the upper half of the secondary winding 2 of the input transformer 1 and the additional secondary winding 3, the capacitor 9 is the first quarter the period is charged across the circuit: load M, upper half of secondary winding 2, additional secondary winding 3 of input transformer 1, semiconductor diode 5. At the same time, transistor 7 is closed, because its collector is supplied with a negative voltage created by the current flowing through the semiconductor, diode 5. For the second quarter of the period, capacitor 9 is discharged along the circuit; the transistor 7, the upper half of the secondary winding 2 of the input transformer I, the load 11. With a negative half-wave, the semiconductor diode 5 and the transistor 7 are closed, and the voltage on the capacitor 9 is zero. The form of the voltage on the capacitor 9 and, consequently, of the charge flowing through it, is represented in Fig. 28 by a solid line.

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The dotted line in FIG. 2 represents the processes occurring in the other half of the push-pull circuit. The current in the load I1 is equal to the sum of the time-differentiated charges flowing through the capacitors 9 and 10 (Fig. 26). Since the current spectrum contains components with frequencies. 2y, Aso, bi ..., then using as a load in general 22

In addition to bandpass filter, you can select the power of the required multiplicity a lot: In this case, there is no direct current in each of the halves of the push-pull circuit and in the load, i.e. the power of the constant component is zero.

Thus, in the proposed frequency multiplier, due to the absence of a constant component, the efficiency

BUT

Claims (1)

A FREQUENCY MULTIPLIER, containing two semiconductor diodes, one of the same electrodes of which are connected to the corresponding terminals of the input secondary winding Fig. 1 of a transformer, the middle point of which is connected to one output terminal of the load, which is so that, in order to increase the efficiency, two transistors, two additional secondary windings of the input transformer and two capacitors are introduced into it, with each capacitor connected between by another terminal of one of the semiconductor diodes and a second terminal of the load, each additional secondary winding of the input transformer is connected between the base and emitter of one of the transistors, and the collector and emitter of each transistor are connected to the corresponding etstvuyuschim heteronymic electrodes of one of the semiconductor diodes. “ZZ55nT” ns 1116