SU1109926A1 - Binary signal-to-quasi-ternary signal converter - Google Patents

Abstract

A BINARY SIGNAL TO A QUASITROICHIC SIGNAL, containing two elements AND, whose outputs through the corresponding single-sided shapers of the pulses are connected to the inputs of the combining unit of two streams of single-sided pulses, the output of which is the output of the converter, characterized by the fact that, in order to protect the immunity of the protection, it is not protected from being protected from being protected from being protected from being protected from being protected by interference and protected. conditions of the effect of transient disturbance, modulo two modulators, two triggers with a counting input, an inverter and a reversible counter, the counting input of which oh combined with the first inputs of the first and second elements And the input of the inverter and is the input of the converter, the output of the inverter through the first trigger with a counting input connected to the first input of the adder mod two, to the second input of which through the second trigger with a counting input the transfer output of the reversible counter is connected, to the control input of which, as well as i, to the second input of the first element I, the direct output of the adder is connected via (L module two, the inverse output of which is connected to the second input of the second. I. yu

Description

The invention relates to telecommunications, in particular, to digital transmission systems (DSPs), using cable lines or lines of other types, equipped with self-timed quad-signal regenerators. In such systems, the original binary signal (CID) for transmission over a line is converted (encoded) into a balanced quasi-triple signal, which can be transmitted without distortion through separation circuits (for example, transformers), which inevitably are in the transmission line, and after transmission, the inverse transformation is performed quasi-tropic signal (decoding) into a binary signal A balanced quasi-tread signal is a sequence of differently alternating positive, negative and zero x parcels, the positive and negative nye pasylki presents t, Tavlya is dissolved rectangular pulses of equal amplitude. The law of alternating positive and negative premises in a balanced quasitroic signal ensures that all components of the energy spectrum at zero frequency are zero (i.e., the absence of a constant component and suppressing the lower frequencies of the spectrum), which allows it to be transmitted without distortion through the separation circuits. In addition, the energy spectrum of a balanced quasi-black signal also vanishes at frequencies that are multiples of the clock frequency of this signal. A known binary signal transducer is a quasi-trivial signal containing two delay elements, a quasi-triple code driver and a counter, as well as a synchronous switch, the inputs of which are connected to the outputs of the delay elements, and the output of the synchronous switch are connected to the first inputs of the quasi-triple code generator and a counter, the second input of which is connected to the input of the first delay element, while the output of the counter is connected to the second input of the quasitroich code generator and the input of the second delay element til. The disadvantage of the converter is that the energy spectrum

its quasi-tropic signal vanishes only at the extreme frequencies of the frequency band from zero frequency to a frequency equal to the clock frequency. never vanish anywhere within this frequency band. This feature of the spectrum of quasi-black signals does not allow practically to achieve the highest theoretical noise immunity at the reception of these signals. The closest to the invention is a binary signal converter into a quasi-trunking signal containing two AND elements, the outputs of which through the corresponding unipolar pulse drivers are connected to the inputs of the combining unit of two unipolar pulses, the output of which is the output of low noise immunity of a quasi-black signal under the conditions of transient noise. The purpose of the invention is to increase the noise immunity of a quasi-ternary signal under the conditions of transient interference. To achieve this goal, a binary signal converter into a quasitroic signal containing two AND elements, the outputs of which are connected to the inputs of the combining unit of two streams of unipolar pulses through the corresponding drivers of unipolar pulses, modulo two, two a trigger with a counting input, an inverter and a reversible counter, the counting input of which is combined with the first inputs of the first and second elements AND, the input of the inverter and is the input of The user, while the inverter output through the first trigger with a counting input is connected to the first input of the modulo two adder, to the second input of which through the second trigger with a counting input is connected the transfer output of the reversible counter, to the control input of which, as well as to the second input of the first element And a direct output of the modulo two adder is connected, the inverse output of which is connected to the second input of the second element I. In FIG. 1 shows the structural electrical circuit of the proposed converter in FIG. 2 - time diagrams of his work. The converter contains an inverter 1, a reversible counter 2, triggers 3 and 4 with a counting input, an adder 5 modulo two, elements 6 and 7, drivers 8 and 9 of unipolar pulses, and block 10 combining two streams of unipolar pulses. The Converter operates as follows. The pulses of the original binary signal (Fig. 2a) of duration T (T the clock interval of the original binary signal) are fed to the input of inverter 1 and simultaneously to the first inputs of the elements 6 and 7 and the counting input of the reversible counter 2, which must be executed with an even counting module. From the output of inverter 1, the inverted input signal (Fig. 26) is fed to the counting input of the first trigger 3 with the counting input (which can be made as a synchronous trigger, the switching time of which is determined by the clock frequency signal), this trigger is switched from at the end of each a clock interval in which there is a single signal sending at the output of the inverter i.e. zero sending the original binary signal, and its output signal (Fig. 26) is fed to the first input of the adder 5 modulo two. The reverse counter 2 counts the unit premisses of the original binary signal, added each time a unit to the previous value of its internal signal (Fig. 2d), with a single signal value (Fig. 2g) at its control input, or viita each time

a unit from the previous value of its internal signal i (Fig. 20, with a zero signal value (Fig. 2ld) When reaching any extreme state (N 2), the reversible counter 2 outputs at its transfer output a single signal send (Fig. 2o). Reverse counter 2 can be executed as a synchronous reversible counter, the moment of switching of which is determined by the clock frequency signal. The signal (Fig. 2o) from the transfer output of the reversible counter 2 is fed to the counting input of the second trigger 4 with a counting input, which can also be Full as a synchronous trigger point shift which is determined by

la, which coincide with the value 1 of the signal at the forward output of the adder 5 modulo two, and the output of the second element And 7 passes (Figure 2K) those pulses of the original binary signal that coincide with the value O of the signal at the direct output of the adder 5 modulo two. The signal from the direct output of the adder 5 modulo two controls the counting direction of the reversible counter 2. The pulses of the signals (Fig. 2 m, k) then go to the inputs of the formers 8 and 9 of the single polarity pulses, respectively. Each driver of unipolar pulses in response to each pulse at its input generates at its output a rectangular pulse with a long clock signal. This trit; the ger switches at the end of each clock interval, in which there is a single premise of the transfer sigal (Fig. 2), and from its output a signal (Fig. 2e) is fed to the second input of the adder 5 modulo two. The binary output signal at the forward output of the adder 5 is modulo two (Fig. 2.) Takes the value 1 (high potential) if there are different signal values at its inputs, i.e. O and 1 or 1 and O. If there are two identical values of signals on the two inputs of the adder 5, i.e. O and O or 1 and 1, then the modulo two admittance of the direct output of the adder is O (low potential). The signal (Fig. 2h) ) at the inverse output of the adder 5 modulo two is always opposite to the signal at the direct output of the adder 5 modulo two, i.e. value 1 the signal at the inverse output of the adder 5 modulo two always coincides with the value O of the signal at the forward output of the adder 5 modulo two and vice versa, therefore, the signal (Fig. 2i) changes simultaneously with the signal (Fig.). Signals from the direct and the inverse outputs of the adder 5 modulo two are fed to the second inputs of the first and second elements, respectively, 6 and 7, and the signal from the direct output of the adder 5 modulo two is also fed to the control input of the reversible counter. Consequently, the pulses of the original binary signal of 0.5 T, rigidly tied in their temporal position to a specific place within the clock interval (for example, located strictly in its first half), pass through the output of the first element I 6 (Fig. 2I). In order to provide the necessary parameters of the pulses of the generator, it usually uses a clock frequency signal (including), which comes from a synchronous generator, which is common with the source of the binary signal, and has the form of a meander with half-period 0.5 T. Unipolar signals (Fig 2/1 and Fig. 2l), formed at the outputs of the formers 8 and 9, of unipolar (positive) pulses, are combined in block 10 of the combination of two streams of unipolar pulses into one quasi-tertiary signal (Fig. 2k). Block 10 can be a passive device, for example, it can be a two-stroke transformer, in this case the formers 8 and 9 of unipolar pulses must provide the required amplitudes (power) of pulses at the outputs that pass to the output of block 10 combining two single-pole flows pulses. However, in the general case, block 10 may contain signal power amplifiers, and these amplifiers can operate in both linear and key modes.

Obviously, when the pulses of the input source binary signal pass to the output of the first element And 6, then in the signal at the output of the unit 10 combining two streams of unipolar pulses, positive pulses appear, and when the pulses of the original discrete signal pass to the output of the second element And 7 , then negative pulses appear in the output signal, and simultaneously with the change in the polarity of the output pulses, the counting direction of the reversible counter 2 also changes. Control of the polarity of the output pulses and the direction of signal down counter 2 counting occurs by the adder 5, the output signal modulo two. The change of this signal (Fig. 2g) occurs in one of the following two cases. First, the reversible counter 2 reaches one of the extreme states, and at its output an odd number of pulses of the transfer signal appear (clock intervals 4, 8, 17, 22, 28 in FIG. 2),

as a result, the signal value (Fig. 26) at the second input of the adder 5 modulo two (A) changes. Secondly, in the initial binary signal (Fig. 2a) an odd number of zero bursts appears (clock intervals 13 and 20 (Fig. 2), as a result of which the value of the signal (Fig. 2b) on the first input of the adder 5 modulo two (b).

Obviously, a change in the counting direction of the reversible counter 2 due to (A) causes the digital sum, the output signal, to be determined by the expression

t

(l

N (i,

B 1

where dL + 1, if there is a positive pulse (output signal) at the i-th clock interval, Oi -1, if there is a negative pulse at the "-th clock interval; (3 O, if there is no impulse at the -t-th clock interval (zero output signal), it turns out to be limited, moreover, unlike the well-known device, since the counting range of the reversible counter NO 4, INItJ l. (2)

Thus, the predominance of positive or negative pulses cannot accumulate in the output signal, i.e. the output signal of the converter is balanced and, therefore, its energy spectrum must be zero at zero frequency (no constant component) and at frequencies edge frequencies of this signal, which is confirmed by the calculation of the spectrum

A change in the counting direction of the reversible counter 2 due to (B) causes the output pulses separated by an odd number of zero bursts to have different signs. Such a pattern of alternation of the signs of the parcels leads to the fact that, in addition to the described features, the energy spectrum of the output signal of the converter has zero values at frequencies

. (2k + 1) -, K 0,1,2, ...

moreover, in the frequency band the energy of the output signal is concentrated in the lower part of this band.

711099268

Thus, under the conditions of the effect of a transitional binary signal in a quasi-noise at the near end, the proposed transformed signal in the near-end signal enhances the cable by concentrating the energy of this noise signal in the lower part of the frequency band.

Claims (1)

A BINARY SIGNAL CONVERTER TO A QUASITROID SIGNAL containing two AND elements, the outputs of which are connected to the inputs of a unit for combining two streams of unipolar pulses through the corresponding drivers of unipolar pulses, the output of which is the converter output, characterized in that, in order to increase the noise immunity ’'of a quasi-ternary signal 4ΣΗ ^{5 5} .4. Yu > 4 -----— 7 - 7> -J Figure 1 of the effect of crosstalk, it introduced an adder modulo two, two flip-flops with a counting input, an inverter and a reversible counter, the counting input of which is combined with the first inputs of the first and second elements And, the input of the inverter and is the input of the converter, the output of the inverter through the first trigger with a counting input connected to the first input of the adder modulo two, to the second input of which through the second trigger with a counting input the transfer output of the reversible counter is connected, to the control input of which, as well as to the second y input of the first AND gate output line is connected modulo two adder, whose inverted output is connected to the second input of the second .elementa I. SU, „. 1109926