SU1092733A1 - Device for automatic frequency control and digital frequency metering detector - Google Patents

Abstract

I. A device for frequency control, containing a serially connected digital frequency synthesizer, a mixer, an intermediate frequency amplifier and a digital frequency detector, and a reference frequency block connected to the second input of the digital frequency synthesizer, the second mixer input being the signal input of the device, characterized in that, in order to increase the sensitivity, the output of the digital frequency meter detector is connected to the first input of the digital frequency synthesizer through the adder and the second output of the reference frequency block is connected to the second input of the detector-measuring1 | frequency, the second input of the adder is the installation input of the predicted frequency value. 2. Digital detector-frequency meter, containing 1; 1 st shape. tel of zero-crossing pulses. the input of which is the first input of the detector-meter, the persistent storage device, the first adder and the series-connected quadr and decisive unit, the output of which is the output, will detect the l-meter, characterized in that, in order to increase the sensitivity, entered, therefore connected counter separator and synchro O15, with the counter-divider input connected to the output of the zero-intersection pulse spinner, and the second synchronizer input connected to the second detector Ithel between the second input and a detector -izmeritel address input of PROM devices included sequentially introduced counter, .registr first, second adder, the switch & To the second bit inputs of which are connected to the outputs of the corresponding bits of the counter, and the second register, the outputs of the bits of which are additionally connected to the second inputs of the bits N0 of the second adder, the outputs of the permanent storage device are: the third register is connected to the perg: the input of the first adder, between the output of the first adder and the first input of the quad, the fourth register, the random access memory and the fifth register are sequentially included, the bit outputs of which are additionally connected us to a second input of said first adder, said second and third inputs decisive ka are respectively input, and setting the detection threshold nacha-, flax a detector installation -measurable;

Description

the fourth, fifth, sixth, seventh and eighth inputs of the decision block, gating the inputs of the first, second, third, fourth and fifth registers, the control input of the switch, the mode setting input and the address inputs of the random access memory, the control The fixed inputs of the permanent storage device and the quad are connected to the corresponding outputs of the synchronizer.

3. Detector-meter according to Claim 2, characterized in that the solver unit contains a series-connected switch, a first register, a comparison unit, the output of which through the OR element is additionally connected to the gate input of the first register, the second register

the adder and the third register, the outputs of which are outputs of the decoupling unit and connected to the second inputs of the adder, as well as the counter, the outputs of the bits of which are connected to the inputs of the corresponding bits of the second register, the second inputs of the comparison unit being combined with the first inputs of the switch and are the first the inputs of the decision block, and the second inputs of the switch, the combined inputs of setting the second and third registers to zero, strobe the inputs of the third register and the comparison block, the counter inputs, the second input of the OR element and channeling kitsy input switch are respectively the second, third, fourth, fifth, sixth, seventh and eighth inputs deciding unit.

The invention relates to radio engineering and can be applied, in particular, to radio receiving devices that communicate with a moving object, to select a signal with a time varying carrier frequency.

A device for automatic frequency control is known, comprising a sequentially controlled oscillator, a mixer, the second input of which is a signal input of the device, and a selective intermediate frequency amplifier, a reference oscillator and a digital period meter. The frequency tuning of the controlled oscillator of this device is performed both at the input of the initial frequency setting in proportion to the corresponding code and in the feedback circuit proportional to the difference between the set and measured values of the duration of the unit period of the transient frequency. This stabilizes the value of the intermediate frequency C 1.

However, this device has low sensitivity: in practice, the device is operational only with a high signal-to-noise ratio at the intermediate frequency amplifier.

The closest to the proposed is a device for frequency control, containing serially connected digital frequency synthesizer, a mixer, the second input of which is a signal input of the device, an intermediate frequency amplifier and a detector, as well as a block of reference frequencies. The detector switches the device from the input detection mode, in which the digital frequency synthesizer is controlled by the initial frequency setting code, to the tracking (trim) mode, in which the digital frequency synthesizer is controlled by the received signal. This solution allows us to narrow the bandwidth of the amplifier intermediate frequency often 2 D.

However, the detector of the known device is outside the frequency-controlled loop and only controls the mode of operation of this ring. With the capture of a signal with a rapidly varying frequency during the transition time of the signal detection mode in the watchdog mode, the latter can change dramatically, which necessitates some expansion of the IF band and the corresponding

Decrease - the sensitivity of the device.

A signal frequency detector is known that contains a serially connected clock, a reversible counter, a storage unit, a sign generation unit and a number conversion unit, an adder unit, a quad and a decision unit, the read enable input of the storage unit connected to the output of the zero-intersection pulse generation unit , and the sign of the output of the counter is connected to the control input of the character forming unit and the conversion of the number C 3.

The hardware volume of said device is determined mainly by the volume of the storage unit and the accumulator accumulator unit. The storage unit must store samples of 2M reference signals calculated for time values te (0, T / 2) in 4t 1 / f steps, i.e. matrix of 2M P binary numbers, where M 2FT is the number of frequency channels of the device: 2F is the width of the analyzed frequency P is the number of clock pulses decreasing by half the observation interval of duration T

The closest in technical essence to the proposed is a digital frequency detector-meter, containing a zero-crossing pulse generator, whose input is the first detector input, a constant memory device, the first adder and a series-connected quadrator and decisive block whose output is The output of the detector 4.

The hardware volume of this device is somewhat less than the previous one due to a decrease in the information capacity of the permanent storage device (encoder). However, the accumulating adders block also contains 2M accumulating adders. There are a large number of permanent memory devices and quadrants (in K sshhd the disadvantage of known frequency detectors, the low utilization rate of the computing equipment and, as a result, the sensitivity is not high enough for a fixed volume. Indeed, the permanent memory devices and accumulative adders perform one

After the formation of each null-inaccuracy and quadrature pulse generator cycle, one cycle is at the end of the observation interval, while the follow-up period of the zero-intersection to be processed for many practical cases (for example, in a device for frequency tuning with prediction value) can significantly exceed the duration of the operating cycles of the detector-meter nodes.

The purpose of the invention is to increase the sensitivity.

This goal is achieved by the fact that in the device for automatic frequency control, containing a serially connected digital frequency synthesizer, a mixer, the second input of which is the signal input of the device, an intermediate frequency amplifier and a digital frequency detector, and a reference frequency block connected to the second the input of the digital frequency synthesizer, the output of the digital detector of the frequency meter through the adder is connected to the first input of the digital frequency synthesizer, and the second output of the reference frequency block The voltage is connected to the second input of the frequency meter detector, the second input of the adder is the input of setting the predicted frequency value.

In a digital detector-frequency meter containing a zero-crossing pulse shaper, whose input is the first input of the detector-meter, a constant storage device, the first sum of the matrix and the series-connected quadrator and the decisive unit, the output of which is the output of the detector-meter, entered in series are the counter-divider and synchronizer, the counter-divider input being connected to the zero-crossing pulse driver output, and the second synchronizer-input input. There is a second counter detector input, a second counter, a first register, a second adder, a switch, the second bit inputs of which are connected to the outputs of the corresponding counter bits, and a second register, outputs the bits of which are additionally connected to the second inputs of the bits of the second adder, the outputs of the permanent storage device are connected to the first input of the first adder via the third register, between the output of the first adder and the first input of the quadrant, the fourth register, the operational memory and the fifth register are sequentially included, the bit outputs of which are additionally connected to the second input of the first adder, the second and third inputs of the decision block are respectively the inputs for setting the detection threshold and the initial installation detector meter, and the fourth, fifth, sixth, seventh and eighth inputs crucial block, gating inputs of the first second, third, fourth and fifth regist The ditch, the control input of the switch, the mode setting input and the address inputs of the random access memory, the control inputs of the permanent storage device and the quadrator are connected to the corresponding outputs of the synchronizer. The decisive block contains a serially connected switch, the first register, a comparison unit, the output through the OR element is connected to the gate input of the first register, the second register, the adder and the third register, the outputs of which are the outputs of the soldering unit and connected to the second inputs of the adder, and also, a counter whose bit outputs are connected to the inputs of the corresponding bits of the second register, the second inputs of the comparison unit being combined with the first inputs of the switch and being the first inputs of the decision unit, and the second inputs of the switch, the combined inputs of zeroing of the second and third registers, the gating inputs of the third register and the comparison unit, the inputs of the counter, the second input of the OR element and the control input of the switch are the second, third, fourth, fifth, the sixth, seventh and eighth inputs of the decision block. In the proposed device for automatic frequency control, the detector, unlike the prototype, is directly connected to the frequency-controlled loop and, in addition to detection, performs the functions of a discriminator, i.e. a measurer of the difference between the actual and predicted value of the frequency of the signal, specified as a code. The result of the frequency difference measurement is continuously added to the target frequency, and the sum is used to control the frequency of the digital synthesizer. Due to the combination of the detection function and frequency measurement in one device, there is no loss of time for the transition from the detection mode to the tracking mode. This, as well as the continuous input of targeting, including in the trailing mode, makes it possible to significantly compensate for the change in the frequency of the signal and reduce the bandwidth of the frequency control device and digital filters of the detector, which leads to an increase in the sensitivity of the proposed device compared to the prototype . The drawing shows the structure-t on the electrical circuit of the proposed devices for automatic frequency control and frequency measurement detector. A device for frequency control contains ring-connected digital synthesizer 1 frequencies, a mixer 2, the second input of which is a signal input of the device, an amplifier 3 of intermediate frequency, a detector-meter frequency 4 and an adder 5, the second input of which is an input for setting the predicted frequency value, as well as a block of reference frequencies 6, the first and second outputs of which are connected to the second inputs of a digital frequency synthesizer and a frequency measuring detector. The frequency detector contains serially connected shaper 7 zero-crossing pulses, the input of which is the first input of the detector, a counter-divider 8, a synchronizer 9, and also a serially connected counter 10, the input of which is the second input of the detector, the first register 11, the second adder 12, switch 13, second register 14, read-only memory 15, third register 6, first adder 17, fourth register 18, random access memory 19, fifth register 20, quad 21 and solver

block 22, where the quad contains a permanent memory device 23, a register 2A, and an adder 25, and the deciding unit contains between the first input and output a serially connected switch 26, a second one. the input of which is the input of the detection threshold, the first register 27, the comparison unit 28, the output of which is additionally connected through the gate OR 29 to the gate. the input of the first register, the second register 30, the adder 31 and the third register 32, the input of which is set to zero is combined with the same input of the second register and the input of the initial installation of the detector, as well as the counter 33.

The device-t automatic frequency control works as follows.

The input signal with carrier frequency f is fed to one input of mixer 2, to the second input of which a heterodyne signal is fed with frequency f from digital synthesizer 1 frequency. The frequency of digital synthesizer 1 is determined by the frequency of the signal coming from the 6 reference frequency block, and at the stage of detecting the input signal, the initial frequency setting code arrives at the control input of digital frequency synthesizer 1 through the adder 5. The other input of the adder 5 comes from the detector output -. frequency meter zero code set by applying a pulse to the input of the initial installation of the detector. .

The intermediate frequency amplifier extracts from the output signal of the mixer a harmonic component with a difference frequency, n}, and "pce (-Po + P), where o is the nominal value of the intermediate frequency, F is the maximum prediction frequency of the input signal.

A 4 meter frequency detector, equivalent to a parallel connection of a set of bandpass filters, the bandwidth of each of which is much less than the intermediate frequency amplifier 3, analyzes the w p signal of the latter. By comparing the output effect of the filters with the detection threshold set as a code on the corresponding input and between themselves, the detector-meter decides whether the input signal is present and also gives an estimate of the maximum likelihood f p of the intermediate frequency i. An estimate of the prediction error of the input signal frequency ij, - {Q, generated at the output of the measuring detector in the parallel binary code, is added in the first adder 5 with the predicted value code and changes the frequency f p of the digital synthesizer 1 such that (j. Thus input detection and tracking

5 for its frequency.

Detector izperterntel frequency works as follows.

B the moment of intersection of the zero level intermediate frequency signal

0 with a positive derivative, a foryor 7 generates a short pulse arriving at the input of the counter of the divider 8, which carries out the division of the pulse frequency

5 null-intersections an integer number, defined by the ratio of the frequency bandwidth of the amplifier 3 prome. Of the frequency. Thinned null-intersection pulses.

0 the first input of the synchronizer 9, to the second input of which is fed from the second output of the block 6 of the reference frequencies, the clock pulses with the following frequency fr Q + F are also fed to the counter 10. In the synchronizer 9, the zero-crossing clock pulses are synchronized by delaying the latter by time, not exceeding the quantization step D-t 1 / ...

Synchronized zero-crossing pulses and other output pulses of the synchronizer 9 arrive at the corresponding times at the inputs of the measuring detector nodes, controlling its operation.

The algorithm for processing a sequence of synchronized zero-crossing pulses consists, first, in the formation of a discrete analogue in the observation interval (O, T)

0 squared modulus of a complex correlation integral on a discrete set of frequencies e () N

2

S

e

g i M

(one)

(d -F | + (t - l) uf are the reference

frequencies; M. 2G / L +; Af “I / 2T is the sampling rate of the frequency; N is the number of synchronized pulses zero intersections arriving during the observation interval OD; tfl (arrival times of synchronized zero-intersection pulses; secondly, find the frequency fnu at which 2 (dj J receive the largest value exceeding the detection threshold. The pulses of the clock frequency f arriving at the counting input of the counter 10 change state periodically its P binary bits with a period of Tr P 1 / d. Determined by the discharge bits of the counter J 0 the number h 12.1 where n is the number of pulses of the clock frequency received at the input of the counter in time-t is associated with the current phase value Signal signal sin 2 ITd-f t in accordance TvstuL (iy moment of time by the relation; 2ld 2Rp / 2 2L;, U where 1 is an integer. At time t, the synchronized zero-intersection pulse allows writing to the P-bit first register 11 of the state P of the counter bits 10 - the number n "/ 2 - and through f,;". - and through switch 13 to the higher bits of the second empty register 14 of the 14 state To the lower bits of the counter 10, the number hn = 2, which is associated with: phase 2 Jf (gP ) t of the reference signal SM 2ff (o-RI ratio of% -ln% / 2 2Jrs. (3) where 5 is an integer,. l / fto-f). The fulfillment of relations (2) and (3) is ensured by the selection of the corresponding frequencies,,. and bit size of the Rig. Following this, the signal of the synchronizer 9 switches the switch 13 to pass the output signal of the second adder 12, and to the gate input of the second register 14 is fed from the synchronizer 9 series of (m-O gating pulses. As a result of the repeated summation by the second adder 12 in the second 13JO register 14 the numbers {tn p-T- .. 7F- (lf}., (41, where {х5 is the fractional part of the number associated with the phase of the reference signal by the relation 2f n n 2 (V) n (- l l ff,, ,., where I is an integer. The consistency of the M numbers (4) is the address of m, at which from the permanent storage device 15 are alternately read into the third register 16 and are fed to one input of the adder 17. real cos2π.f and imaginary Sfn part of the function exp (), e: 1; lH. From the output of the adder 17 through the buffer quarter register 18 according to the corresponding 2M Addresses of the operative storage device 19 are recorded as the results of addition n n./2 Vn. (Y: instead of the previous amounts C f p ,, and obtained from the operational storage device 19 to the buffer. Fifth fifth register 20 and fed to the second input of adder 17, with 4.0 O, (1, M). The calculations of M numbers (4 | and the corresponding 2M sums (6) end before the next one arrives (zero-intersection pulse to synchronizer 9 after which the whole cycle is repeated. Thus, almost immediately after the arrival of the latter, the accumulation results I - JL-: .N, t, 5 ,,, are recorded in the random access memory in the observation interval (DD | N of the zero-crossing pulse) After that, the synchronizer 9 converts the detector-frequency meter from the accumulated mode and in the mode of searching for the maximum of the correlation integral modulus: the synchronizer 9 writes the number to the counter 33 and to the register 27 through the switch 26 of the detection threshold, switches the switch 26 to pass the output signal of the accumulator 25 and reads Cg, e 1, alternately in the register 20 m from the random access memory 19. The latter serve as addresses from which their squares are read from the permanent storage device 23, fed to the inputs of the adder 25 directly (sl) to via the d-switch 24 (c | ). Each of M forms a ruem at the output of adder 25 is the value of the square of the correlation module 2 () s | The j Cff integral is compared with the contents of register 2 in the gated comparison unit 28. If any value Z (j) exceeds the contents of register 27, then the strobing pulse of synchronizer 9 passes from the input and output of the comparator unit 23 and allows writing the corresponding value () to the register 27 through switch 26 and the counter status register 30 the counter 33 after the cache; the comparison clock cycle is increased by 1, thus taking a number of Mf values. . . --- 2- {е- (| ---, t, M, i.e. from -F / 4 at :-( to F / djE REM. If the input signal of the pfiK device does not automatically adjust the frequency or its level is below the threshold, then none of the numbers 2 (ft 1, M does not exceed the detection threshold, there are no pulses at the output of the comparison block 28 and the register 30 saves the zero state. When a signal is detected, the correction value () / d is recorded in the register 30 | f 1 / L, corresponding to the most possible one of M of the numbers) g (c). The correction to the output register 32 is entered by the synchronizer 9 after viewing all M numbers 2 (fg) | for all about the time, how much one of N calculation cycles of sums (61 i.e. less than T / N "T at.. Thus, the detector-meter 10 3 frequency is equivalent to parallel connection of matched filters with a bandwidth of 2D € 1 / T each, overlapping the 2F range of the prediction error of the input signal frequency. A distinctive feature of the proposed frequency measurement detector is the more efficient use of functional units in comparison with the known devices. Thus, the persistent storage device and the first adder perform 2M 1 duty cycles after each processed pulse and an intersection, the aquadrator holds M duty cycles at the end of each observation interval. Due to this, increasing the volume (RAM capacity 2M), the size of the adders and RAM of the proposed measuring meter to the volume of the prototype device, you can increase the signal accumulation time T in the device, and hence its sensitivity. The sensitivity of the proposed device for automatic frequency control is limited by the requirement that the signal level exceeds the interference level, in contrast to the known device, not in the passband of the intermediate frequency amplifier, which cannot be less than 2F, but in the 2L band (and therefore, at M1, the sensitivity of the previous device and the reliability of entering synchronization is much higher than the known. Since N, then at M the time of signal detection and transition to the tracking mode T + T / N T is almost the minimum possible when implementing the required sensitivity of the device / Tests conducted on prototypes of the proposed device with parameters: {, kHz, 5 kHz, M 128, T 12.5 ms, 2P gave the following results. The sensitivity of the proposed device, characterized by the ratio of the power of the useful signal to the interference power is about I2 + -I3 dB in the 2d? iSO in band with a probability of 0.9 signal detection and transition to the tracking mode during 12.5 ms. ,

Claims (3)

1. Device for automatic frequency control, containing a series-connected digital frequency synthesizer, mixer, intermediate-frequency amplifier and a digital detector-frequency meter, as well as a block of reference frequencies connected to the second input of the digital frequency synthesizer, the second input of the mixer being the signal input of the device, characterized in order to increase the sensitivity, the output of the digital detector of the frequency meter through the adder is connected to the first input of the digital frequency synthesizer, and the second the output block of the reference frequencies is connected to the second input of the detector-frequency meter, the second input of the adder is the input of the installation of the predicted value of the frequency. 2. A digital detector-frequency meter containing a forming- ·. The zero-crossing pulse generator, whose input is the first input of the detector-meter, is constant. a memory device, a first adder and a series-connected quadrator and a deciding unit, the output of which is the output of a detection meter, characterized in that, in order to increase the sensitivity, a subsequently connected counter-divider and synchronizer are introduced into it, and the counter input is the divider is connected to the output of the zero-intersection pulse shaper, and the second synchronizer input is connected to the second input of the detector-meter, between the second input of the detector-meter and the constant address input of the memory device, the input counter, the first register, the second adder, the switch, the second bit inputs of which are connected to the outputs of the corresponding bits of the counter, and the second register, the outputs of the bits of which are additionally connected to the second inputs of the bits of the second adder, the outputs of the permanent memory, are sequentially connected devices through the third register are connected to the first input of the first adder, between the output of the first adder and the first input of the quad, the fourth register is connected in series, random access memory and the fifth register, the bit outputs of which are additionally connected to the second input of the first adder, the second and third inputs of the decisive unit ·: ka being the inputs of the detection threshold and the start. Flax detector installation -measure-: about s Saz> tel, and the fourth, fifth, sixth, seventh and eighth inputs of the decisive block, the gate inputs of the first, second, third, fourth and fifth registers, the control input of the switch, the mode setting input and address inputs of random access memory, the control inputs of read-only memory and quad connected to the corresponding outputs of the synchronizer. 3. The detector-meter according to claim 2, characterized in that the decision unit comprises a series-connected switch, a first register, a comparison unit, the output of which, through an OR element, is additionally connected to the gate input of the first register, the second register * 'adder and the third register, outputs 'which are the outputs of the decisive; unit and connected to the second inputs of the adder, as well as a counter whose outputs are connected to the inputs of the corresponding bits of the second register, the second inputs of the comparison unit combined with the first inputs of the switch and are the first inputs of the deciding unit, and the second inputs of the switch, the combined installation inputs to zero the second and third registers, the gate inputs of the third register and the comparison unit, the counter inputs, the second input of the OR element and the control input of the switch are respectively the second, third, four The third, fifth, sixth, seventh and eighth inputs of the decisive block.