SU1076902A1 - Array device for implementing multiplication - Google Patents

Abstract

MATRIX DEVICE FOR A MULTIPLE LIFE, containing three multipliers, a buffer adder and an output adder, with the low-order bits of the first and second device operands connected to the inputs of the first multiplier, the high-level inputs of the first and second devices of the device are connected to the inputs of the second multiplier, the first and second inputs The multipliers are connected to the inputs of the bi-adder and respectively the first and second groups of inputs of the output adder, characterized in that, for the purpose of simplification, it contains two input su mmator and subtractor, the inputs of the first input adder are connected to the high and low bits of the first operand of the device, the inputs of the second input adder are connected to the high and low bits of the second operand of the device, the outputs of the first and second input deviators are connected to the inputs of the third multiplier, the outputs of the third multiplier and the buffer adder are connected to the inputs of the transmitter, the outputs of which are connected to the third group of inputs of the output adder.

Description

The invention relates to digital computing and is used in high-speed arithmetic devices of universal and specialized digital computers.

A digital multiplier of 2p-digit numbers is known, which contains a chetrlre and n-bit multipliers and a three-input Zn-times adder ij

The drawbacks of the device are the complexity and high cost associated with the use of four expensive AND -disk multipliers.

The closest to the proposed is a matrix device for multiplying, containing, reg-isters of a multiplier and a multiplier, two additional registers, two units of forming partial products and three units of summing partial products with the outputs of the multiplicable and multiplier registers connected to the first and second groups of inputs the first block of the formation of partial products whose outputs are connected to the inputs of the first block of summation of partial products, the outputs of the first and second additional registers are connected to the first and second group of inputs of the second block of formation of partial products, respectively, the outputs of which are connected to the inputs of the second block of summation of partial products, the outputs of which are connected to the first group of inputs of the third block of cyMji-shirovania partial works of the second and third groups of inputs are connected to the first and second groups the outputs of the first block summation part chn: -lx products, respectively, 2,

A disadvantage of the known device is the difficulty associated with the fact that not all partial products are products of positive numbers. This necessitates the availability of additional funds for working with numbers that have a sign, and complicates the formation units and the sum of the partial works about

The purpose of the invention is to simplify the device.

The goal is achieved by the fact that the matrix, a multiplication device containing three multipliers, a buffer cyMTJiaTop and an output sum of 1.AT9P, and the low-order inputs of the first and second operands of the device are connected to the inputs of the first multiplier, the high-level inputs of the first and second operands of the device are connected with the inputs of the second multiplier, the outputs of the first and second multipliers are connected to the inputs of the buffer adder and, respectively, with the first and second groups of inputs of the output adder, contain two input adders and a calculator the input of the first input adder is connected to the inputs of the high and low bits of the first operand of the device; the inputs of the second input adder are connected to the inputs of the high and low bits of the second operand of the device; the outputs of the first and second input adders are connected to the inputs of the third multiplier, the outputs of the third the multiplier and the buffer adder are connected to the inputs of the subtractor, the outputs of which are connected to the third group of inputs of the output adder.

The drawing shows a functional diagram of a matrix device for multiplication.

The device contains the first, second and third multipliers 1-3, the first and second input adders 4 and 5, the buffer adder b, the output adder 7 and the subtractor 8 The device has inputs 9 and 10 of the low and high bits of the first operand and inputs 11 and 12 the low and high bits of the second operand. The output 13 is the output of the device.

The device works as follows.

Let and and be, respectively, the first unused bits of the 2d bit of the first first operand / .- and And ij, U (2 are the And junior and n high-order bits of the 2n-bit second operand, respectively. At the outputs of the input adders 4 and 5, respectively we get

5i U, + U2-, + Vj.

On the outputs of multipliers 1-3, the corresponding products are formed

, - U, V, - P2 - U2 4) P9S-, Q

At the outputs of the buffer adder 6, subtractor 8 and the output sum.

5z R. РЗ 5, Рэ-5э-, 5в 4P. PaU25.

At the output 13 of the output adder 7 really get the desired product

about (and, 2 (M ,.

The multipliers used in the device are multipliers of non-negative numbers, thereby eliminating the need for tools to work with numbers that have a sign.

Compared with the basic object, which is a matrix multiplier, which is part of a large integrated circuit KR587IKZ 3 BKO.348.569-ОЗТУ, the proposed matrix multiplier for bounds, for example, 32x32 contains 11% fewer gates. 10769024 The economic effect from the implementation of the invention per one multiplier is 11 rubles. by reducing the number of vents.

Claims (1)

(5 7) A MATRIX DEVICE FOR MULTIPLICATION, comprising three multipliers, a buffer adder and an output adder, the inputs of the least significant bits of the first and second operands of the device being connected to the inputs of the first multiplier, the inputs of the senior bits of the first and second operands of the device being connected to the inputs of the second multiplier , the outputs of the first and second multipliers are connected to the inputs of the buffer adder and, respectively, with the first and second groups of inputs of the output adder ·, characterized in that, for the sake of simplification, it contains two input sums a torus and a subtracter, and the inputs of the first input adder are connected to the inputs of the highest and lowest bits of the first operand of the device, the inputs of the second input adder are connected to the inputs of the highest and lower bits of the second operand of the device, the outputs of the first and second input adders are connected to the inputs of the third multiplier, § the outputs of the third the multiplier and the buffer adder are connected to the inputs of the calculator, the outputs of which are connected to the third group of inputs of the output adder.