SU1053266A1 - Frequency discriminator - Google Patents

Description

The invention relates to radio engineering and can be used in radio receivers of frequency modulated signals.

A frequency detector is known that contains two adders, the first inputs of which are connected to the input source through a delay line and a phase inverter, and the others directly, and the outputs of both adders are connected via amplitude detectors with inputs of a subtractor ij.

However, this frequency detector has insufficient detection accuracy.

The closest in technical essence to the invention is a frequency detector comprising a delay line, a phase inverter connected in series, a first adder and a first amplitude detector, connected in series a second adder and a second amplitude detector, and a third adder and subtraction unit, whose inputs are connected to the outputs of the first and a second amplitude jpoB detector, wherein the phase inverter inputs and the delay line, as well as the first input of the second adder are combined and are the input of the frequency detector and the output the delay line is connected to the second inputs of the first and second adders 2.

However, in the known frequency detector, when exposed to spurious amplitude modulation of the input signal, the detection accuracy decreases.

The purpose of the invention is to improve the detection accuracy when exposed to spurious amplitude modulation of the input signal.

The goal is achieved in that a frequency detector containing a delay line, a phase inverter connected in series, a first adder and a first amplitude detector are connected in series to a second one. the adder and the second amplitude detector, as well as the third adder and the deduction block, whose inputs are connected to the outputs of the first and second amplitude detectors, the phase inverter inputs and the delay line, as well as the first input of the second adder, are the frequency detector stroke, and the output of the delay line is connected to the second inputs of the first and second adders, a DC elimination block and a serially connected division block, a multiplication block and an additional subtraction block, whose output is the output of the frequency detector, with a first input and a second input dividing unit further subtractor unit connected to the output of the subtractor block of the third adder output is connected to the second input of the block dividing unit and the input of eliminating D.C. output of which is connected to the second input of the multiplying unit.

The drawing shows a structural electrical circuit of the proposed frequency detector.

The frequency detector contains phase inverter 1, delay line 2, first and second adders 3 and, first and second amplitude detectors 5 and 6, third adder 7, subtraction unit 8, division unit 9, multiplication unit 10, lox 11 for eliminating the constant component and additional block 12 subtraction.

Frequency detector (BH) works as follows.

The frequency-modulated signal from the input source is fed through the delay line 2 and the phase inverter Top 1 to the inputs of the adders 3 and. The signal from the ZIL adders output, detected by the amplitude detectors 5 and 6, is fed to the inputs of the first subtractor 8 and the inputs of the third adder 7. As a result of the parasitic amplitude modulation of the input signal, the output signal of the first subtraction 8 subtraction is also romodulated according to the amplitude modulation of the input signal

U, .- A-F (, (1)

where A is a constant coefficient; F (tV is the useful signal; M (t) is the parasitic amplitude signal

moduli

Similarly, at the output of the third sum 7

U ,, (2) where B is a constant coefficient Signals and ,, and 1. C come to the input of block 9, at the output of which u..rub (3 V From (3) it follows that the signal at the output of block 9 division does not depend on the input signal level, since const, and thus the influence of parasitic modulation is eliminated. As mentioned, the real division blocks have a high level of non-linear distortion, which does not allow the output signal of the dividing circuit to be used as the output of the BH- despite the fact that it lacks the influence of spurious amplitude modulation. The purpose of the invention is achieved by the fact that the signal from the output of dividing unit 9 is used only to obtain a compensating signal by subtracting which from the output of the first subtracting unit 8, compensation for the change in the level of the output signal is obtained when the input signal level changes. the nonlinear properties of dividing unit 9 only affect the compensating signal, which is much smaller than the useful signal, the BH linearity is high with high noise immunity. The signal at the output of block 9 is equal to U.Y A-FWl-- | -nt, (1). (4l function that determines the nonlinear distortion of dividing unit 9, for A-RapA We represent (1) as U ,.- AF (t) iA-Wit) -F (tb (5) Here, the first term determines the useful output signal , and the second signal is interference from the influence of parasitic amplitude modulation. Similarly, from (2) we get and, B + 8.M1M. () Block 11 extracts from (6) the MW signal. (7) From CO and (7) we have a signal at the output of block 10 multiplication U, -U.-U .F (tV) r AF {0 -GA (U -A-WvitbFW FW, (8) A comparison (8) and (5) shows that (8) with an accuracy determined by the nonlinearity of dividing unit 9, is a signal of interference in the output signal of the first b subtraction lock 8. Subtracting from (8) the expression (5) is obtained. we get. -Ux-A F (t) aW (l) x P (tl-U-) r ft-FW V Comparison of expressions (5) and (9 ) shows that the signal interference at the output of the second subtraction unit 12 is m times smaller, where A.ShF (tl A.Wlit) F (t) 4 ytA-FWl Thus, the proposed RR has noise immunity from the effect of spurious modulation m times more, compared to the baseline BH. (9) will be used to estimate the nonlinear distortion of the output signal. Let us estimate the nonlinearity of the output signal as the ratio of the increment of the output signal of the BH due to the nonlinearity of the dividing circuit to the useful output signal. Let the error of block 9 division 5, then 1 - 5.: A - F (t) g / 1 + a In the case of an ideal block 9 division (8 0) out of 9 we have. |: (TbA.NAlt) -F (tKH) .AF (t). (11) In the case of a non-ideal dividing unit 9 (), the output signal is determined by formula (9). From (9) and (10) we determine the output signal increment. Due to the nonlinearity of the unit 9 of the division UA-llJ2 - U2l- | AF (t) -AF (t) -A-MUVF (iV and -VtAF ((t) ( (t)) l; From (10) and (11), we estimate the nonlinear distortions caused by the nonlinearity of the block 9 dividing A-Nv (Mf (tVU-y A. A-PW. I)) y |, 03)) H Considering that w «x. for (1) .8.1 oooc. (1 /) wax Using (T), we will conduct a numerical estimate of the introduced nonlinear distortion in the output of the BH due to the nonlinearity of the division block 9. For this, we will specify the following practical values: the nonlinearity of the dividing scheme 5 ± 0.03 (3); The spurious amplitude modulation depth of the input signal is 5%, i.e. W (.t) 0.05. From (1) we have 0 ,. Thus, the nonlinearity of the dividing unit 9 leads to an increase in the nonlinearity of the output signal by only 0.15, which is much less, the nonlinearity of the base frequency detector, by 1-2%, and therefore the proposed RR practically retains the linearity of the basic device -2%. At the same time, from (10) we have A-Nb-iBiyu.oz-and-Usa-tsits about. The proposed BH has, by comparison with the baseline, more than 30 times higher noise immunity with respect to the parasitic amplitude modulation of the input signal.

Claims (1)

FREQUENCY DETECTOR, soder- _x zhaschy, delay line sequential ;, but connected phase inverter, a first adder and a first amplitude detector, a second adder connected in series and the second amplitude detector, and a third adder and a subtractor whose inputs are connected to outputs of the first and second amplitude detectors, while the inputs of the phase inverter and the delay line, as well as the first input of the second adder. are combined and are the input of the frequency detector, and the output of the delay line is connected to the second inputs of the first and second adders, characterized in that, in order to increase the accuracy of detection when exposed to spurious amplitude modulation of the input signal, a block to eliminate the DC component and sequentially connected division block are introduced into it , the multiplication unit is an additional subtraction unit, the output of which is the output of the frequency detector, with the first input of the division unit and the second input of the additional unit you readings are connected to the output of the subtraction unit, the output of the third adder is connected to the second input of the division unit and the input of the elimination unit of the constant component, the output of which is connected to the second input of the multiplication unit. >