SU1045239A1 - Device for graphic information readout - Google Patents

Abstract

- DEVICE FOR READING -. GRIPHIC INFORMATION NII contains the first Trigger, whose inputs are connected to the first delay element and to the output of the first OR element, one input of which is the first input of the device, the second element of S1I, one input of which is the second input of the device, and the output connected to the first element delays, an element whose inputs are connected to a clock pulse generator and to the output of the first trigger, and the output is connected to one input of the first switch, the other input of which is connected to the output of the second trigger, .a output The first switch s are connected to one input of the second and third switches, the other inputs of which are connected by the output of the third trigger, a driver connected to the output of the first trigger and one input of the cathode ray tube, the other inputs of which are connected to the respective units of the beam deflection, row counter, connected to the second switch, to one input of the first comparison unit, the other input of which is connected to the inverter, to the first input of the second comparison unit, the second input of which | Go is connected to the output the house of the first. trigger, with one beam deflection unit and one input of the memory unit, the second input of which is the third input, and the output output of the device, respectively, the third and fourth elements OR, frame counter, connected to the third switch, with the third input of the first element OR, with an inverter, with the third input of the memory block, with another block of deviation, and with the third input of the comparison block, the VC code of which is connected to one input of the fifth OR element, the output of which is connected to one input of the second trigger, and one thing (f) of the third flip-flop, and the selector, characterized in that, in order to increase the speed of the device, it contains a third element, a delay, HfcHi is connected to the selector and to another input of the fifth OR element, in this case. the inputs of the third element OR are connected to the second delay element and the second switch, and the output is connected to another input of the row counter, the inputs of the fourth element N9 OR are connected to the third switch and the second delay element, m and the output is connected to the second input of the frame counter, The second output of which is connected to the second delay element, to the other input of the first OR element, and to another input of the second OR element, the output of which is connected to another input of the second trigger, to the third inputs of the row and frame counters, toromu input of the third flip-flop, a third input coupled to the second delay element and the selector inputs are connected to outputs of the first AND element and comparing unit.

Description

The invention relates to automation and computing technology and can be used as a means of reading graphic information from photo carriers (microfilm, microfiche) in information and information retrieval systems for inputting it into a digital computer or for transmitting it to a display device.

A device is known which comprises a first trigger connected to a delay element, a first WN element, an AND element connected to a pulse generator and a signal conditioner connected to a cathode ray tube associated with the beam deflection blocks X and Y, a second trigger, connected to the first switch connected to the element AND to the second AND third switch. connected to the third trigger and to the summing inputs of the row and frame counters, respectively, the comparison unit connected to the selector named pulse, a second OR gate, .sravneni unit connected to the selector .impulsov, a memory unit coupled to the frame counters strok.i podklyuchennymik beam deflection units posootvetstvuyuschim coordinates 1 ..

In this device, the reading of graphic information is carried out by a spiral-rectangular scan starting from the center of the frame, which reduces the time to read the image. The drawing configuration can be obtained only when the CRT beam scans the entire frame area limited by the overall contour of the part (node), which significantly reduces the speed of the device.

Closest to the present invention is a device comprising a first trigger connected to the first. the OR element, with the first element | 3-delays connected to the second element OR, with the AND element connected to the clock generator and with a signal conditioner connected to the electron-beam tube, the first switch connected to the And element, with the second trigger connected to the third element or and the second and third mmutatami connected to the third trigger, the row counter the summing input of which is connected to the second switch, and the output with the power unit, with the first and second comparison blocks and with the power unit rejected and the beam along the X coordinate, connected to the CRT, the frame counter, the summing input of which is connected to the third switch / and the output to the second comparison unit connected to the first trigger, to the gateway element S1I and to the third trigger, to the memory block, to the block the deviation of the beam along the coordinate connected to the CRT, the inverter connected to the first block and the frame counter, the second delay element, the pulse selector, the fourth and fifth elements

OR 2. . :.

In a known device, information is read by scanning an image frame by

squares of various sizes, which allows to obtain the configuration of the drawing long before the end of the scan of the entire area of the read frame. However, when moving from one square of scanning to another, the CRT beam is carried out for the time required for the beam to reach the scanning start point located on the diagonal of the read frame, i.e. there is a reverse (ve working) beam path. At the same time, the damping time of the beam is a constant value equal to the maximum time required for the beam to pass from; the scan start point of one square to the most distant scan start point of another square, which reduces the speed of the device, as for example, for ten-bit line and frame counters, the number of reverse moves is 512. In addition, during the square scan, the beam returns to the starting point scan, which leads to re-reading this point.

 The purpose of the invention is to increase the speed of the device by using a scan in the form of two rectangular spirals.

The goal is achieved by the device containing the first trigger, the inputs of which are connected to the first delay element and the output of the first OR element, the input of which is the first input of the device, the second RSHI element, one input of which is the second input device, and the output is connected to the first delay element, the element I, the inputs of which are connected to the clock pulse generator and the output of the first trigger, and the output is connected to the one input of the first switch, the other input of which is connected to the output of the second th flip-flop, and the outputs of the first switch are connected to one .The inputs of the second and third switches, the other inputs of which are connected to the output of the third trigger signal generator coupled to the output of the first flip-flop and to one input of a cathode ray tube,

the other inputs of which are connected to the corresponding beam deflection blocks, the row counter connected to the second switch / to one input of the first comparison unit, the other input of which is connected to the inverter to the first input of the second comparison unit, the second input of which is connected to the output of the first trigger, with one block beam deflection and with one input of the memory unit, the second input of which is the third input, and the output is the device output, respectively, the third and fourth elements OR, frame counter, connected to the third switch ohm, with the third input of the first, OR element, with an inverter, with the third input of the memory unit, with another beam deflection unit and with the third input of the comparison unit, the output of which is connected to one input of the fifth element, OR, the output of which is connected to one an input of the second trigger, i.e to one input of the third trigger, and a selector comprising a third delay element connected to the selector and to the 1st input of the fifth OR element, wherein the inputs of the third OR element are connected to the second delay element and to the second switch, and output connected to OTHER INPUTS row count, inputs of the fourth element OR are connected to the third switch and the second delay element, and the output is connected to the second frame counter input, the second output of which is connected to the second delay element, to the other input of the first OR element and to the other input of the second OR element ,: whose output is connected to another input of the second trigger, to the third inputs of row and frame counters, to the second input of the third trigger, the third input of which is connected to the second delay element, and the selector inputs are connected to the outputs of the first AND elements and the comparison block.

FIG. 1 shows a block diagram of the device, FIG. 2 -3 - hodographs are shown. The CRT beam, which explains the principle of operation in FIG. 4, is the spatial areas of the frame, showing the effect obtained.

The device contains a generator of 1 clock pulses, the first element 2 delay, the first element OR 3 / element AND 4, the first trigger 5, in the second element OR, the first switch 7, the second trigger 8, the third trigger 9, the second and third kVM-mutators 10 and 11, third and fourth; th elements OR 12 and 13, counter 14 lines, counter 15 frames, second delay element 16, third delay element 17, selector 18

pulses, the first comparison unit 19, the inverter 20, the fifth element OR 21, the second comparison unit 22, the OJiOK 23 beam deflection along the X coordinate, the driver of the 24 signals, the deflection block 25, the beam along the Y coordinate, memory block 26, CRT 27, the first, second and third inputs 28-30 of the device and the output 31.

The first trigger 5 is connected to

0 delay element 2, and the first WLI 3 element, AND 4, which is connected to the output of the 1 clock pulse generator, to the second comparison unit 22, and to the driver

5 24 signals connected to CRT 27. The output of the second element OR 6 is connected to. the first element is 2 delays, with the second and third triggers 8 and 9 and with counters of 14 lines and 15 frames. The first switch 7 under the 0 keys to the AND 4 element, connected to the pulse selector 18, to the second trigger 8, connected to “1 element OR 21, to the second and third switches 10 and 11,

5 connected to the third trigger 9. The second switch 10 is connected to the summing input of the counter of 14 lines and to the third element OR 12 connected to the subtractive input of the counter of 14 lines, and the third switch 11 is connected to the summing input of the counter of 15 frames and to the quarter element OR 13.,. connected to the subtracting input of the counter 15 kad5 ditch. A counter of 14 rows is connected to a memory unit 26, with the first comparison unit 19, connected to the pulse selector 18, with the second unit. : 22 comparisons, connected to the p element OR 21 and to the third

0 trigger 9, with a beam deflection block 23 along the X coordinate connected to CRT 27. A 15 frame counter is connected to a second delay element 16 connected to the third and fourth elements OR 12 and 13 and to the third trigger 9, with memory block 26 connected to the output 31 of the device, with an inverter 20 connected to the first block 19 of the comparison, with the first and second elements OR 3 and 6, with the second block 22 of the comparison and with the block 25 of the deflection of the beam on the coordinate Y connected to the ELG 27. 18 pulse selector

5 is connected to a third delay element 17 connected to the OR OR 21 terminal. The first, second and third inputs 28-30 of the device are connected to the first OR 3 element, respectively, to the second U1I bis element by a memory block 26.

The device works as follows.

The turn-on signal, input 29, passes through the element OR 6 and sets the triggers 8 and 9 to the state O, writes the unit to the higher bits of the counters 14 and 15, and also enters the input of the element 2 delay. As a result of the recording, at the outputs of the counters 14 and 15, the code 100o..O (one in the higher order) is removed, which enters the corresponding blocks 23 and 25 of the beam deflection along the X and Y coordinates and determines the deflecting current of the CRT 27 equal to the fault of the maximum current (the maximum current corresponds to the code 111 ..,) Since the trigger 5 at the initial moment is in the state O, then at the output of the driver 24 connected to the CRT module 27 there will be a damping signal (the closing modulator ). Consequently, the extinguished beam moves to the center of the screen, to point A (Fig. 2, where the numbers show the contents of the three-bit counters 14. and 1; Sf marks the direction of the beam movement with arrows). The turn-on impulse, pro1 element 2, posteriorly, sets the trigger 5 to state 1. This results in the shaper 24 switching off the extinguishing beam signal and the beam of the CRT 27 illuminated, and the And 4 element is allowed to pass pulses Oscillator 1 on switch 7, Delay on element 2. It is necessary for the beam of ELT27 to go to the center of the screen before it lights up. Since triggers 8 and 9 are in state O, KoiviMyTaTop 7 is connected to switch 11 , and switches 10 and 11 through the elements OR 12 and 13, respectively, to the subtractors (- } to the inputs of counters 14 and 15, Therefore, the first impulse, which appeared at the output of the element I 4, goes through the switches 7 and 11 and the element OR 1 to the (-) - input of the counter 15 kr.drov and reduces its content by one, as a result At the output of the counter 15, the code 011 "..1 appears; it moves to point B (Fig. 2). At the output of the inverter 20, the code is set to .100 .., O, Since the content of the counter is 14 lines (code 100. ,, 0 does not change, then at the output of the comparison block 19, there appears a pulse that enters the pulse selector 18, intended, iyiH to extract a single pulse and navlivaet that in its initial state i.e. permits the allocation of a single pulse from a sequence of pulses coming from the vsod of the element OR So, the second pulse from the output of the AND 4 element is selected by the selector 18 and fed to the input of the delay element 17. Simultaneously, the second clock pulse. from the output of the element And 4. passes through the switches 7 and 11 and the element OR 13 to () the input of the counter 15 cal-: and reduces its content by another one. On. The output of the counter 15 is set to the code OH, .. 10 and the beam moves to point B (Fig. 2). The clock pulse selected by the selector 18, which appeared at the output of the delay element 17, passes through the OR element 21 and arrives at the counting input of the trigger 8 , changes its state to the opposite. As a result, trigger 8 is set to state 1, and switch 7 switches to a co-switch 10. Delay on element 17 is necessary for the clock pulse to be counted by counter 15 before switch 7 switches , Regular clock pulses. l (the third, fourth from the output of the element And 4 arrive through the switches 7 and 10 and the element OR 12 on. (-) 15. 14 counter INPUT until the contents of the counters 14 and 15 coincide "At CRT beam CRT 27 variable: given in point G, (fig. 2) 5 and counters 14 and 15 will be in code 011 ,,., .. 10, In cut, the output at the output of the comparison unit 22 appears and, The impulse, which is supplied, and the counting input is three, and 9, and through the OR element 21, the counting input of the trigger 8 and. and changes their state to the opposite. As a result, the trigger. 9 becomes 1 and switch switches 10 and 11 to the summing inputs (-) of counters 14 and 15, and the trigger -8 enters the state O and the TfOMJ-iy switch (fifth, ..) from the output of the element I 4 through ko: & utatory 7 n 11 postunay pa () counter input 15 n successively increase the content of the beam of the CRT 27, is transmitted to the EG, Fig, 2, It is the ORIGINAL to those So far, the search for the By:; 1 ° block is, and 19 is not a comparison, Wits, h BUT, BE it, while this CRT beam 27 is at point D. 1-1mpls C from: Bykoda b, Lock 19 again enters, ss, e, r1vktor 18 ;, which allocates about, the single clock clock of the choir, switches KOMfviyTa.Top 7 to switch 10, and, changing the state of trigger 8 to the opposite, and () the counter input 15kA, the clock comes another clock impu; bc, This beam is p CRT 27 leschaets-inflection. At point E (FIG. 2), Sredozate, Pno, Ocherdnke, clock pulses arrive through a commutator 7 to 10 on (} the counter-villain 14 lines and increase its content. This process proceeds until 14 and Ib is not iB ST, the beam will move by W (Fig. 2). As a result, the impulse that has been changed in the state, i and m q, they returned to their initial state, Le Oh, while the switch 7 is re-connected with (-) the inputs of the counters 14; xGi scanning is repeated. IF, during the scanning process, the LUCH CRT 27 goes out (falls). nGlean and POINT graphic The second osmayi is a video signal that overwrites the contents of counters 14 and 15 into memory block 26. From the block 23, the coordinates of the--read points are output to the device output 31 by means of the signals received from the graphic-information-reading devices lasts until the Padrov counter is completely filled, consequently, on the –o –yo yjej G - ;; d-; b..o: With this, the BEAM of the CRT is at point 3 (Fig. 2). At the output of block 19, a comparison of the Wits p2d impulse, a post to the selector 18 and one more tact YOU impulse from the output of the element 4 will be recorded in counter 15, In the overflow counter of the counter 15 frames (transition to the 11 ... i state) 00 ,,. 0) at its output is a transfer pulse that passes through the OR 3 element and sets the rigger 5 to the O state. As a result, the CRT beam 27 dampens the AND 4 element and closes to pass the clock ° momentum to the input of the element 16 delay and passing the element OR 6 again records the unit in the senior 1 4 and 15, coor 8 and 9 to the state O and arriving at the input of the delay element 2 After sweeping on the output of the delay element 16, the transfer pulse sets the trigger 9 to the state 1, and PASSING the elements OR 12 goes to (.) the outputs of counters 14 and 15 and reduces their contents (code 100 and; n1 units, as a result, the sieves of vehicles emerged as code 011 ,, ,, i and the extinguished beam moves to the center of the screen, but not to point I (FIG. , 3), and switches 10 and 11 are connected to; 7 1Gz1d1rzhka inputs of counters 14 and 15. Delay nGelement 16 is necessary in order for the transfer pulse managed to write the unit to the higher bits of counters 14 and 15 before it ..eSST; ai: U;, Sr "s ::; ss / n rprs;: CRT 27 is turned on, and the element And 4 ° - ::: G : ;; reading and reading - 2 GGT., Initial moment pulses from the output of the element I 4 arrive, mutators 7 and 11 on the (-) input, and 15 frames, not on the (-) input, as it was before. When the score is reset to Zsna 15 frames in the process of scanning Gluch. is at point k, -fig 3 at its (-) input,. erne one clock pulse ,, At the point of transition of the counter 15 from the state 0 or 00 ... O into the state 11,., 1, at its output, there is a lock that passes through the fL tL element iG 0 ™ So; ecGcch : SILNI - e2 :: Newbies;: nGt of reactive links allows you to increase quickly / the effect of the proposed device.

L

phases. 2

.n

n

fig.Z

about f g 3 V- 5bT83jOf1

±

Z

th &

Z3

Claims (1)

'' DEVICE FOR READING GRAPHIC INFORMATION, containing the first trigger, the inputs of which are connected to the first delay element and to the output of the first OR element, one input of which is the first input of the device, the second OR element, one input of which is the second input of the device, and the output is connected to the first a delay element, AND element, the inputs of which are connected to the clock generator and the output of the first trigger, and the output is connected to one input of the first switch, the other input of which is connected to the output of the second the trigger, and the outputs of the first switch are connected to one input of the second and third switches, the other inputs of which are connected ^ With the output of the third trigger, a signal conditioner connected to the output of the first trigger and to one input of the cathode ray tube, the other inputs of which are connected to the corresponding beam deflection units, a line counter connected to the second switch, to one input of the first comparison unit, the other input of which is connected to the inverter, to the first input of the second comparison unit, the second input of which it is single with the output of the first trigger, with one beam deflection unit and with one input of the memory block, the second input of which is the third input, and the output is the device output, respectively, the third and fourth elements OR, a frame counter connected to the third switch, with the third input of the first OR element, with an inverter, with the third input of the memory unit, with another beam rejection unit and with the third input of the comparison unit, the output of which is connected to one input of the fifth OR element, the output of which is connected to one input of the second trigger, and to one input of the third trigger, and a selector, characterized in that, in order to improve the performance of the device, it contains a third delay element connected to the selector and to the other input of the fifth OR element, while the inputs of the third OR element are connected to the second delay element and with the second switch, and the output is connected to another input of the counter 'lines, the inputs of the fourth OR element are connected to the third switch and the second delay element, and the output is connected to the second input of the frame counter, the second output of which is connected the second delay element, with a different input of the first OR element and with a different input of the second OR element, the output of which is connected to another input of the second trigger, to the third inputs of the line and frame counters, to the second input of the third trigger, the third input of which is connected to the second delay element , and the selector inputs are connected to the outputs of the first AND elements and the comparison unit.