SU1001479A1 - Integrated logic circuit - Google Patents

Description

(5) INTEGRATED LOGICAL SCHEME

The invention relates to microelectronics and can be used in computing and in a discrete automation system. An inverter is known in which higher speeds are caused by the fact that the steepness of the fronts of the output impulse is preserved and the differential amplitude is reduced by introducing a circuit consisting of several diodes and a Cl 1 transistor. The disadvantage of this inverter is the increased power consumption from the power source a logical 1 and a lower value of the output voltage of a logical one. Also known is a TTL element containing an input multi-emitter transistor, a double emitter phase separation and an output transistor stor, resistors and acceleration circuit. The base of the multi-mitter and the collector of the phase-separation transistors are connected via resistors to the power bus, the collector of the first mentioned transistor is connected to the base of the second one. One emitter of the phase-rotation transistor is connected to the base of the output transistor and through a common bus resistor, the second emitter is connected to the collector of the output transistor with an accelerating circuit and an output of the element. A disadvantage of the known element is that through the transistor of the accelerating circuit, when the output transistor is turned on, significant pulse currents flow, while the base current of the said transistor is limited by a resistor connected between the collector of the phase separation transistor and the power supply bus, which cannot be reduced Since this leads to an increase in power consumption, the above circumstances lead to an increase of. The switching time of the output transistor and the increase in power consumption with increasing switching frequency (due to the development of surge current surges), as well as limiting the load capacity in the logical O state. The purpose of the invention is to reduce power consumption and increase the high-speed load capacity. The goal is achieved in that the integrated logic circuit containing the input multiemitter transistor, the base of which through a resistor is connected to the power bus, the collector to the base of the phase separation transistor, the collector of which is connected to the power bus through the resistor and the base of the transistor accelerating circuit, the collector which through the resistor is connected to the power bus, the emitter through the diode to the collector of the output transistor and the BMXOAOMJ emitter of the output transistor is connected to the common bus, an additional transistor to the collector of which is connected to the power supply bus, the base is connected to the emitter of the phase-separation transistor, through an additional diode with the collector of the output transistor and through the series-connected diode and resistor to the common bus, the emitter of the additional transistor is connected through corresponding resistors to the common bus and the biasing of the output transistor , while the collector of the output multiemitter transistor is connected to its base. The drawing shows the scheme of the device. The device contains an input multi-emitter transistor 1, the base of which is connected to a power source through a resistor 2 and a phase-separation transistor 3, whose collector is connected to a power source through a resistor C. The base of the transistor 3 is connected to the collector and the base of the transistor 1. In the circuit there is an accelerating circuit consisting of transistor 5i, the base of which is central to the collector of transistor 3, the collector through resistor 6 to the power source, and the emitter to diode 7, the cathode of which connected to the output 8 and the collector of the output transistor 9, the emitter of the transistor 9 is connected to the common supply bus, the collector of the additional transistor 10 is connected to the power source, the base is connected to the emitter of the transistor 3, with the anode of the additional diode 11 whose cathode To the output 8, and with the resistor 12, the second end of which is connected to the anode of the diode 13, the cathode of which is connected to the common bus, the emitter of the transistor 10 is connected to the resistors T and 15, the second ends of which are connected respectively to the common power bus and the base of the transistor 9- The emitters of transistor 1 are connected to the device. The proposed device works as follows. If a part of the inputs 16 (or all) is supplied with a low voltage level, the phase separation transistor 3 is closed, therefore, the output transistor 3 is also closed, since no current flows into its base, and the output 8 of the circuit has a high voltage level. If a high voltage level is applied to all inputs 1b, the phase separation transistor 3 will open and a current will flow through it that will branch out: part will flow into the circuit consisting of resistor 12 and diode 13, and partly into the base of transistor 10 connected according to the emitter circuit repeater. In this case, an excess current is set in the base of transistor 9, which ensures its fast switching on, and the magnitude of this excess current can be quite significant and is limited, practically, only by a resistor 15, whose resistance is made small. At the initial moment of time when the transistor 9 has not yet turned on, the current through diode 11 cannot flow and the voltage drop across resistors i and 12 are approximately equal. The voltage at the base of the transistor 5 decreases rapidly, which also contributes to a faster switching on of the output transistor 9. As soon as the output transistor 9 turns on and the voltage on its collector becomes equal to. The voltage drops on the straight pn junction through diode 11 a current begins to flow out (a common 1 part of the current from the base of the additional transistor 10 to the collector part of the output transistor 9. Thus, the current required through the transistor 10 flows only to create a fall on the resistor 14

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a voltage equal to the forward voltage drop across the base-emitter junction of the output transistor 9 and the base current of the transistor 9.

This reduces the base current of the transistor 10 and its value is determined by the gain of the transistor 9 and all the excess current flows through the diode 11 into the collector of the transistor

Thus, the limitation of the degree of appreciation of the output transistor 9 is reduced, because the resistor k can be relatively large in this case, since it does not determine the magnitude of the base current of the transistor E. As well as increasing the load capacity of the circuit in the logical state Oh, because as the load current increases, part of the current, flowed through diode 11, is redistributed to the base of the additional transistor 10 and causes an increase in the base current of the transistor 9 16 strokes (or all) re-create a low uroben voltage, transistor 3 turns off, the current to the base of the output transistor stops, and since there is no excess base current, output transistor 9 turns off quickly. At the same time, there will be a significantly smaller inrush current when the circuit is turned off through the boost circuit.

Claims (1)

1. USSR author's certificate number 305587, cl. H 03 K 19/00, 1976. 2, Shagurin And, And. Transistor-Transistor Logic Circuits, N., Soviet Radio, 197, p. 96, rice 3, (prototype).