SG99328A1 - Method, system, program, and data structures for transforming an instruction in a first bit architecture to an instruction in a second bit architeture - Google Patents

Method, system, program, and data structures for transforming an instruction in a first bit architecture to an instruction in a second bit architeture

Info

Publication number
SG99328A1
SG99328A1 SG200100114A SG200100114A SG99328A1 SG 99328 A1 SG99328 A1 SG 99328A1 SG 200100114 A SG200100114 A SG 200100114A SG 200100114 A SG200100114 A SG 200100114A SG 99328 A1 SG99328 A1 SG 99328A1
Authority
SG
Singapore
Prior art keywords
instruction
bit
architeture
transforming
program
Prior art date
Application number
SG200100114A
Other languages
English (en)
Inventor
Ontko Jackson Andrea
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG99328A1 publication Critical patent/SG99328A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/52—Binary to binary

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Devices For Executing Special Programs (AREA)
SG200100114A 2000-01-14 2001-01-05 Method, system, program, and data structures for transforming an instruction in a first bit architecture to an instruction in a second bit architeture SG99328A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/483,203 US6662361B1 (en) 2000-01-14 2000-01-14 Method, system, program, and data structures for transforming an instruction in a first bit architecture to an instruction in a second bit architecture

Publications (1)

Publication Number Publication Date
SG99328A1 true SG99328A1 (en) 2003-10-27

Family

ID=23919104

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200100114A SG99328A1 (en) 2000-01-14 2001-01-05 Method, system, program, and data structures for transforming an instruction in a first bit architecture to an instruction in a second bit architeture

Country Status (7)

Country Link
US (1) US6662361B1 (de)
EP (1) EP1118933A3 (de)
JP (1) JP3606561B2 (de)
KR (1) KR20010086328A (de)
CN (1) CN1127688C (de)
SG (1) SG99328A1 (de)
TW (1) TW494361B (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7024666B1 (en) * 2002-01-28 2006-04-04 Roy-G-Biv Corporation Motion control systems and methods
US20010032278A1 (en) 1997-10-07 2001-10-18 Brown Stephen J. Remote generation and distribution of command programs for programmable devices
US8032605B2 (en) 1999-10-27 2011-10-04 Roy-G-Biv Corporation Generation and distribution of motion commands over a distributed network
US6880069B1 (en) * 2000-06-30 2005-04-12 Intel Corporation Replay instruction morphing
US7904194B2 (en) 2001-02-09 2011-03-08 Roy-G-Biv Corporation Event management systems and methods for motion control systems
US6819270B1 (en) * 2003-06-30 2004-11-16 American Express Travel Related Services Company, Inc. Method and system for universal conversion of MCC, SIC or other codes
US20060064503A1 (en) 2003-09-25 2006-03-23 Brown David W Data routing systems and methods
US8027349B2 (en) 2003-09-25 2011-09-27 Roy-G-Biv Corporation Database event driven motion systems
CN100345136C (zh) * 2004-06-30 2007-10-24 中国科学院计算技术研究所 使64位处理器兼容32位桥接芯片的系统及转换装置
US7437541B2 (en) * 2004-07-08 2008-10-14 International Business Machiens Corporation Atomically updating 64 bit fields in the 32 bit AIX kernel
CN100388195C (zh) * 2006-02-22 2008-05-14 北京金山软件有限公司 一种64位视窗操作系统下获取函数参数的方法及系统
US9652210B2 (en) * 2007-08-28 2017-05-16 Red Hat, Inc. Provisioning a device with multiple bit-size versions of a software component
US8832679B2 (en) * 2007-08-28 2014-09-09 Red Hat, Inc. Registration process for determining compatibility with 32-bit or 64-bit software
US10120663B2 (en) 2014-03-28 2018-11-06 Intel Corporation Inter-architecture compatability module to allow code module of one architecture to use library module of another architecture
WO2017153815A1 (en) * 2016-03-11 2017-09-14 Lzlabs Gmbh Load module compiler
CN107423084B (zh) * 2017-04-24 2021-02-02 武汉斗鱼网络科技有限公司 程序修改方法及装置
CN109491659B (zh) * 2017-09-11 2022-06-21 龙芯中科技术股份有限公司 指令转换方法和装置
JP2019095952A (ja) * 2017-11-21 2019-06-20 ソニーセミコンダクタソリューションズ株式会社 プロセッサ、情報処理装置および処理方法
US20220374236A1 (en) * 2021-05-20 2022-11-24 Huawei Technologies Co., Ltd. Method and system for optimizing address calculations
KR20240025509A (ko) * 2022-08-17 2024-02-27 베리실리콘 마이크로일렉트로닉스 (상하이) 컴퍼니 리미티드 크로스 링크 방법, 장치, 전자 설비 및 저장 매체

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568630A (en) * 1991-03-11 1996-10-22 Silicon Graphics, Inc. Backward-compatible computer architecture with extended word size and address space
US5710731A (en) * 1996-05-07 1998-01-20 International Business Machines Corporation Combined adder and decoder digital circuit
US5774694A (en) * 1996-09-25 1998-06-30 Intel Corporation Method and apparatus for emulating status flag

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04500132A (ja) * 1988-07-29 1992-01-09 ハンター・システムズ・ソフトウェア・インク ２進符号の機械語のプログラムを別の２進符号の機械語に翻訳する機械処理
EP0651321B1 (de) 1993-10-29 2001-11-14 Advanced Micro Devices, Inc. Superskalarmikroprozessoren
US5781750A (en) * 1994-01-11 1998-07-14 Exponential Technology, Inc. Dual-instruction-set architecture CPU with hidden software emulation mode
US5577231A (en) * 1994-12-06 1996-11-19 International Business Machines Corporation Storage access authorization controls in a computer system using dynamic translation of large addresses
US5826089A (en) 1996-01-04 1998-10-20 Advanced Micro Devices, Inc. Instruction translation unit configured to translate from a first instruction set to a second instruction set
US5842017A (en) * 1996-01-29 1998-11-24 Digital Equipment Corporation Method and apparatus for forming a translation unit
US5819067A (en) 1996-02-23 1998-10-06 Advanced Micro Devices, Inc. Computer system configured to translate a computer program into a second computer program prior to executing the computer program
US5875318A (en) 1996-04-12 1999-02-23 International Business Machines Corporation Apparatus and method of minimizing performance degradation of an instruction set translator due to self-modifying code
US5875336A (en) 1997-03-31 1999-02-23 International Business Machines Corporation Method and system for translating a non-native bytecode to a set of codes native to a processor within a computer system
US6009261A (en) * 1997-12-16 1999-12-28 International Business Machines Corporation Preprocessing of stored target routines for emulating incompatible instructions on a target processor
US6199202B1 (en) * 1998-01-06 2001-03-06 Hewlett-Packard Company Method and apparatus for the inter-operation of differing architectural and run time conventions
US6018799A (en) * 1998-07-22 2000-01-25 Sun Microsystems, Inc. Method, apparatus and computer program product for optimizing registers in a stack using a register allocator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568630A (en) * 1991-03-11 1996-10-22 Silicon Graphics, Inc. Backward-compatible computer architecture with extended word size and address space
US5710731A (en) * 1996-05-07 1998-01-20 International Business Machines Corporation Combined adder and decoder digital circuit
US5774694A (en) * 1996-09-25 1998-06-30 Intel Corporation Method and apparatus for emulating status flag

Also Published As

Publication number Publication date
KR20010086328A (ko) 2001-09-10
US6662361B1 (en) 2003-12-09
JP2001216169A (ja) 2001-08-10
CN1127688C (zh) 2003-11-12
TW494361B (en) 2002-07-11
JP3606561B2 (ja) 2005-01-05
EP1118933A3 (de) 2004-04-07
EP1118933A2 (de) 2001-07-25
CN1306245A (zh) 2001-08-01

Similar Documents

Publication Publication Date Title
SG99328A1 (en) Method, system, program, and data structures for transforming an instruction in a first bit architecture to an instruction in a second bit architeture
IL144449A0 (en) Method and system for providing buffer management in a performance enhancing proxy architecture
AU6686701A (en) System and method for linking information in a global computer network
AU2001261141A1 (en) Method and system for achieving high availability in a networked computer system
AU4365801A (en) Method and system for secure payments over a computer network
GB2373085B (en) Method, computer program and system for style sheet generation
GB2384886B (en) System and method for securing a computer
AU2001237965A1 (en) Method, system and computer software for providing a genomic web portal
GB0323780D0 (en) A data brokering method and system
AP1945A (en) A data aquisition unit, system and method for geophysical data
AU2002243376A1 (en) System and method for scheduling and executing data transfers over a network
AU2001227599A1 (en) Operating system having a system page and method for using same
AU2001266987A1 (en) System and method for enabling non-volatile memory to execute code while operating as a data storage/processing device
AU6243701A (en) Method for making secure a typed data language in particular in an integrated system and integrated system therefor
HK1052994A1 (zh) 降低對能量(高壓交流電)(hvac)需求的電腦程序及方法
EP1280353A4 (de) System und verfahren zur lieferung von information und programm, welches einem rechner ermöglicht, das verfahren auszuführen
AU2002221394A1 (en) Method and apparatus for reducing latency in a memory system
GB0521374D0 (en) A method and apparatus to improve multi-CPU system performance for access to memory
AU2001255651A1 (en) System and method for using a page tracking buffer to reduce main memory latencyin a computer system
AU2001261451A1 (en) System and method for performing a synchronization operation for multiple devices in a computer system
AU2001284237A1 (en) Method and system for generating performance data
AU2001298114A1 (en) Method and computer program for single instruction multiple data management
AU3571001A (en) Control system and method in a computer environment
AU2003259189A1 (en) Method, system, and program for returning data to read requests received over a bus
AU2001287655A1 (en) Method, computer program, and system for carrying out a project