SG84516A1 - Area efficient realization of coefficient architecture fir, iir filters and combinational/sequential logic structure with zero latency clock output
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Area efficient realization of coefficient architecture fir, iir filters and combinational/sequential logic structure with zero latency clock output
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Application filed by St Microelectronics Pte Ltd, Sgs Thomson MicroelectronicsfiledCriticalSt Microelectronics Pte Ltd
Publication of SG84516A1publicationCriticalpatent/SG84516A1/en
SG9804190A1997-10-151998-10-13Area efficient realization of coefficient architecture fir, iir filters and combinational/sequential logic structure with zero latency clock output
SG84516A1
(en)
Method and arrangement in a transposed digital fir filter for multiplying a binary input signal with tap coefficients and a method for disigning a transposed digital filter
Method and arrangement in a transposed digital fir filter for multiplying a binary input signal with tap coefficients and a method for disigning a transposed digital filter
Area efficient realization of coefficient architecture for bit-serial fir iir filters and combinational/sequential logic structure with zero latency clock output
AREA EFFICIENT MANUFACTURE OF COEFFICIENT ARCHITECTURE FOR BIT SERIAL FIR, IIR FILTERS AND COMBINATORIAL / SEQUENTIAL LOGICAL STRUCTURE WITHOUT LATENCY