SG65572A1 - Bus architecture for integrated data and video momory - Google Patents

Bus architecture for integrated data and video momory

Info

Publication number
SG65572A1
SG65572A1 SG1996005177A SG1996005177A SG65572A1 SG 65572 A1 SG65572 A1 SG 65572A1 SG 1996005177 A SG1996005177 A SG 1996005177A SG 1996005177 A SG1996005177 A SG 1996005177A SG 65572 A1 SG65572 A1 SG 65572A1
Authority
SG
Singapore
Prior art keywords
momory
video
integrated data
bus architecture
architecture
Prior art date
Application number
SG1996005177A
Inventor
James Testa
Edward Frank
Andreas Bechtolsheim
Trevor Creary
David Emberson
Shawn Fontaine Storm
Bradley Hoffert
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of SG65572A1 publication Critical patent/SG65572A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Memory System (AREA)
  • Digital Computer Display Output (AREA)
  • Image Input (AREA)
SG1996005177A 1992-05-19 1993-05-04 Bus architecture for integrated data and video momory SG65572A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/886,671 US5265218A (en) 1992-05-19 1992-05-19 Bus architecture for integrated data and video memory

Publications (1)

Publication Number Publication Date
SG65572A1 true SG65572A1 (en) 1999-06-22

Family

ID=25389504

Family Applications (1)

Application Number Title Priority Date Filing Date
SG1996005177A SG65572A1 (en) 1992-05-19 1993-05-04 Bus architecture for integrated data and video momory

Country Status (6)

Country Link
US (1) US5265218A (en)
EP (1) EP0571099B1 (en)
JP (1) JP3248140B2 (en)
KR (1) KR100219359B1 (en)
DE (1) DE69322310T2 (en)
SG (1) SG65572A1 (en)

Families Citing this family (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270964A (en) * 1992-05-19 1993-12-14 Sun Microsystems, Inc. Single in-line memory module
US5666521A (en) * 1992-12-07 1997-09-09 Intel Corporation Method and apparatus for performing bit block transfers in a computer system
US5572655A (en) * 1993-01-12 1996-11-05 Lsi Logic Corporation High-performance integrated bit-mapped graphics controller
WO1995015528A1 (en) * 1993-11-30 1995-06-08 Vlsi Technology, Inc. A reallocatable memory subsystem enabling transparent transfer of memory function during upgrade
US5454107A (en) * 1993-11-30 1995-09-26 Vlsi Technologies Cache memory support in an integrated memory system
US5450542A (en) * 1993-11-30 1995-09-12 Vlsi Technology, Inc. Bus interface with graphics and system paths for an integrated memory system
US5623506A (en) * 1994-01-28 1997-04-22 International Business Machines Corporation Method and structure for providing error correction code within a system having SIMMs
US5696917A (en) 1994-06-03 1997-12-09 Intel Corporation Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory
WO1995035572A1 (en) * 1994-06-20 1995-12-28 Neomagic Corporation Graphics controller integrated circuit without memory interface
US5838334A (en) * 1994-11-16 1998-11-17 Dye; Thomas A. Memory and graphics controller which performs pointer-based display list video refresh operations
US6067098A (en) * 1994-11-16 2000-05-23 Interactive Silicon, Inc. Video/graphics controller which performs pointer-based display list video refresh operation
US6002411A (en) * 1994-11-16 1999-12-14 Interactive Silicon, Inc. Integrated video and memory controller with data processing and graphical processing capabilities
US5577236A (en) * 1994-12-30 1996-11-19 International Business Machines Corporation Memory controller for reading data from synchronous RAM
JPH08195077A (en) * 1995-01-17 1996-07-30 Internatl Business Mach Corp <Ibm> Transfer system of dram
US5859649A (en) * 1995-05-15 1999-01-12 Motorola, Inc. Data processing system having display controller with bursting direct memory access
US5826043A (en) * 1995-06-07 1998-10-20 Ast Research, Inc. Docking station with serially accessed memory that is powered by a portable computer for identifying the docking station
US5784076A (en) * 1995-06-07 1998-07-21 International Business Machines Corporation Video processor implementing various data translations using control registers
KR100341073B1 (en) * 1995-10-17 2002-08-22 마이크론 테크놀로지, 인크. Memory bus termination module
US5835102A (en) * 1995-10-19 1998-11-10 Sparta, Inc. System for transmission and recovery of digital data using video graphics display processor and method of operation thereof
US5835772A (en) * 1995-12-29 1998-11-10 Intel Corporation Method and apparatus for providing an interface between a system and a peripheral device
US5802603A (en) * 1996-02-09 1998-09-01 Intel Corporation Method and apparatus for asymmetric/symmetric DRAM detection
US5906003A (en) * 1996-04-17 1999-05-18 Cirrus Logic, Inc. Memory device with an externally selectable-width I/O port and systems and methods using the same
US5680365A (en) * 1996-05-16 1997-10-21 Mitsubishi Semiconductor America, Inc. Shared dram I/O databus for high speed operation
US5911149A (en) * 1996-11-01 1999-06-08 Nec Electronics Inc. Apparatus and method for implementing a programmable shared memory with dual bus architecture
US6115318A (en) * 1996-12-03 2000-09-05 Micron Technology, Inc. Clock vernier adjustment
US6195746B1 (en) * 1997-01-31 2001-02-27 International Business Machines Corporation Dynamically typed register architecture
US6067593A (en) * 1997-07-18 2000-05-23 Avido Systems, Inc. Universal memory bus and card
US6084934A (en) * 1997-03-06 2000-07-04 International Business Machines Corporation Natural throttling of data transfer across asynchronous boundaries
US6035371A (en) * 1997-05-28 2000-03-07 3Com Corporation Method and apparatus for addressing a static random access memory device based on signals for addressing a dynamic memory access device
US6058444A (en) * 1997-10-02 2000-05-02 Micron Technology, Inc. Self-terminating electrical socket
US7197575B2 (en) * 1997-12-17 2007-03-27 Src Computers, Inc. Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
US20040236877A1 (en) * 1997-12-17 2004-11-25 Lee A. Burton Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM)
US7373440B2 (en) * 1997-12-17 2008-05-13 Src Computers, Inc. Switch/network adapter port for clustered computers employing a chain of multi-adaptive processors in a dual in-line memory module format
US7565461B2 (en) 1997-12-17 2009-07-21 Src Computers, Inc. Switch/network adapter port coupling a reconfigurable processing element to one or more microprocessors for use with interleaved memory controllers
US6347394B1 (en) 1998-11-04 2002-02-12 Micron Technology, Inc. Buffering circuit embedded in an integrated circuit device module used for buffering clocks and other input signals
US6141710A (en) * 1998-12-15 2000-10-31 Daimlerchrysler Corporation Interfacing vehicle data bus to intelligent transportation system (ITS) data bus via a gateway module
US6338144B2 (en) 1999-02-19 2002-01-08 Sun Microsystems, Inc. Computer system providing low skew clock signals to a synchronous memory unit
JP3722194B2 (en) 1999-05-20 2005-11-30 セイコーエプソン株式会社 Image display system
US6414868B1 (en) 1999-06-07 2002-07-02 Sun Microsystems, Inc. Memory expansion module including multiple memory banks and a bank control circuit
DE19941348A1 (en) * 1999-08-31 2001-03-08 Micronas Gmbh Memory access unit for selectively accessing static or dynamic memory has external address bus used for addressing static memory or dynamic memory in dependence on internal address word
US6567091B2 (en) 2000-02-01 2003-05-20 Interactive Silicon, Inc. Video controller system with object display lists
US6725314B1 (en) 2001-03-30 2004-04-20 Sun Microsystems, Inc. Multi-bank memory subsystem employing an arrangement of multiple memory modules
US6996686B2 (en) * 2002-12-23 2006-02-07 Sun Microsystems, Inc. Memory subsystem including memory modules having multiple banks
KR100520219B1 (en) * 2003-01-03 2005-10-11 삼성전자주식회사 memory module device for use in high frequency operation
US7234099B2 (en) * 2003-04-14 2007-06-19 International Business Machines Corporation High reliability memory module with a fault tolerant address and command bus
US20040268143A1 (en) * 2003-06-30 2004-12-30 Poisner David I. Trusted input for mobile platform transactions
US7725680B1 (en) * 2006-07-06 2010-05-25 Marvell International Ltd. Pipeline interposer
US7752373B2 (en) * 2007-02-09 2010-07-06 Sigmatel, Inc. System and method for controlling memory operations
US8122322B2 (en) 2007-07-31 2012-02-21 Seagate Technology Llc System and method of storing reliability data
US8108761B2 (en) * 2007-08-23 2012-01-31 Intel Corporation Optimizing the size of memory devices used for error correction code storage
US9201790B2 (en) * 2007-10-09 2015-12-01 Seagate Technology Llc System and method of matching data rates
KR101796116B1 (en) 2010-10-20 2017-11-10 삼성전자 주식회사 Semiconductor device, memory module and memory system having the same and operating method thereof
CN104471549B (en) * 2012-06-28 2017-06-16 三菱电机株式会社 Read requests processing unit

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4181933A (en) * 1978-04-18 1980-01-01 Mohawk Data Sciences Corp. Memory access and sharing control system
JPS60245034A (en) * 1984-05-18 1985-12-04 Ascii Corp Display controller
US4701865A (en) * 1984-06-25 1987-10-20 Data General Corporation Video control section for a data processing system
US5185859A (en) * 1985-10-22 1993-02-09 Texas Instruments Incorporated Graphics processor, a graphics computer system, and a process of masking selected bits
US4992960A (en) * 1986-12-11 1991-02-12 Yamaha Corporation Apparatus for processing image data for displaying an image on a display unit
US4959793A (en) * 1987-04-22 1990-09-25 Nec Corporation Microcomputer having function of generating data signals used for displaying characters
EP0288649B1 (en) * 1987-04-22 1992-10-21 International Business Machines Corporation Memory control subsystem
US4980828A (en) * 1988-11-25 1990-12-25 Picker International, Inc. Medical imaging system including use of DMA control for selective bit mapping of DRAM and VRAM memories
JP2910303B2 (en) * 1990-06-04 1999-06-23 株式会社日立製作所 Information processing device
US5283877A (en) * 1990-07-17 1994-02-01 Sun Microsystems, Inc. Single in-line DRAM memory module including a memory controller and cross bar switches

Also Published As

Publication number Publication date
KR100219359B1 (en) 1999-09-01
DE69322310T2 (en) 1999-05-27
US5265218A (en) 1993-11-23
EP0571099B1 (en) 1998-12-02
KR930023842A (en) 1993-12-21
JPH06318182A (en) 1994-11-15
EP0571099A1 (en) 1993-11-24
DE69322310D1 (en) 1999-01-14
JP3248140B2 (en) 2002-01-21

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