SG11202103007XA - Validation processing device, validation processing method, and program - Google Patents

Validation processing device, validation processing method, and program

Info

Publication number
SG11202103007XA
SG11202103007XA SG11202103007XA SG11202103007XA SG11202103007XA SG 11202103007X A SG11202103007X A SG 11202103007XA SG 11202103007X A SG11202103007X A SG 11202103007XA SG 11202103007X A SG11202103007X A SG 11202103007XA SG 11202103007X A SG11202103007X A SG 11202103007XA
Authority
SG
Singapore
Prior art keywords
validation processing
program
processing device
processing method
validation
Prior art date
Application number
SG11202103007XA
Inventor
Kenji Takao
Keita Hirayama
Original Assignee
Mitsubishi Heavy Ind Eng Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Heavy Ind Eng Ltd filed Critical Mitsubishi Heavy Ind Eng Ltd
Publication of SG11202103007XA publication Critical patent/SG11202103007XA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/10—Geometric CAD
    • G06F30/15—Vehicle, aircraft or watercraft design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/02—CAD in a network environment, e.g. collaborative CAD or distributed simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/04—Constraint-based CAD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/06—Multi-objective optimisation, e.g. Pareto optimisation using simulated annealing [SA], ant colony algorithms or genetic algorithms [GA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/08—Probabilistic or stochastic CAD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/02—Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/10—Geometric CAD
    • G06F30/13—Architectural design, e.g. computer-aided architectural design [CAAD] related to design of buildings, bridges, landscapes, production plants or roads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/10—Geometric CAD
    • G06F30/17—Mechanical parametric or variational design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/10—Geometric CAD
    • G06F30/18—Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Aviation & Aerospace Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
SG11202103007XA 2018-11-01 2019-10-03 Validation processing device, validation processing method, and program SG11202103007XA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018206518A JP7214440B2 (en) 2018-11-01 2018-11-01 Verification processing device, verification processing method and program
PCT/JP2019/039133 WO2020090345A1 (en) 2018-11-01 2019-10-03 Validation processing device, validation processing method, and program

Publications (1)

Publication Number Publication Date
SG11202103007XA true SG11202103007XA (en) 2021-05-28

Family

ID=70464004

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202103007XA SG11202103007XA (en) 2018-11-01 2019-10-03 Validation processing device, validation processing method, and program

Country Status (4)

Country Link
US (1) US11347918B2 (en)
JP (1) JP7214440B2 (en)
SG (1) SG11202103007XA (en)
WO (1) WO2020090345A1 (en)

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* Cited by examiner, † Cited by third party
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JP7204609B2 (en) * 2019-07-30 2023-01-16 三菱重工エンジニアリング株式会社 VERIFICATION PROCESSING DEVICE, VERIFICATION METHOD AND PROGRAM
JP7354051B2 (en) 2020-04-13 2023-10-02 三菱重工業株式会社 Hydrogen release/storage systems, hydrogen release/storage methods, ammonia production equipment, gas turbines, fuel cells, and steel plants
JP7345432B2 (en) * 2020-06-03 2023-09-15 三菱重工業株式会社 Verification processing device, verification processing method and program

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JPH07146800A (en) * 1993-11-25 1995-06-06 Hitachi Ltd Rule consistency checking method in agent system and agent system
US5559811A (en) * 1994-09-14 1996-09-24 Lucent Technologies Inc. Method for identifying untestable and redundant faults in sequential logic circuits.
US5566187A (en) * 1994-09-14 1996-10-15 Lucent Technologies Inc. Method for identifying untestable faults in logic circuits
JP3418034B2 (en) * 1995-04-04 2003-06-16 株式会社日立製作所 Event control device and event control method
JPH11149491A (en) * 1997-11-17 1999-06-02 Toshiba Corp Fault detection rate evaluation method
US6067651A (en) * 1998-02-20 2000-05-23 Hewlett-Packard Company Test pattern generator having improved test sequence compaction
US6874135B2 (en) * 1999-09-24 2005-03-29 Nec Corporation Method for design validation using retiming
US20050149301A1 (en) * 1999-09-24 2005-07-07 Nec Corporation Method for design validation using retiming
US7315802B1 (en) * 2003-05-06 2008-01-01 Xilinx, Inc. Methods of logic reduction in electrical circuits utilizing fault simulation
JP4744980B2 (en) * 2005-08-25 2011-08-10 株式会社東芝 Pattern verification method, program thereof, and method of manufacturing semiconductor device
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US20120198399A1 (en) * 2011-01-31 2012-08-02 Sean Arash Safarpour System, method and computer program for determining fixed value, fixed time, and stimulus hardware diagnosis
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US10095813B2 (en) * 2013-11-18 2018-10-09 The Boeing Company Safety analysis of a complex system using component-oriented fault trees
JP2016085152A (en) * 2014-10-28 2016-05-19 富士通株式会社 Diagnostic apparatus, diagnostic program and diagnostic method
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Also Published As

Publication number Publication date
JP2020071759A (en) 2020-05-07
WO2020090345A1 (en) 2020-05-07
US11347918B2 (en) 2022-05-31
JP7214440B2 (en) 2023-01-30
US20220114314A1 (en) 2022-04-14

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