SG11202102246WA - Nanofabrication and design techniques for 3d ics and configurable asics - Google Patents

Nanofabrication and design techniques for 3d ics and configurable asics

Info

Publication number
SG11202102246WA
SG11202102246WA SG11202102246WA SG11202102246WA SG11202102246WA SG 11202102246W A SG11202102246W A SG 11202102246WA SG 11202102246W A SG11202102246W A SG 11202102246WA SG 11202102246W A SG11202102246W A SG 11202102246WA SG 11202102246W A SG11202102246W A SG 11202102246WA
Authority
SG
Singapore
Prior art keywords
nanofabrication
ics
asics
configurable
design techniques
Prior art date
Application number
SG11202102246WA
Inventor
Sidlgata Sreenivasan
Paras Ajay
Aseem Sayal
Mark Mcdermott
Jaydeep Kulkarni
Original Assignee
Univ Texas
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Texas filed Critical Univ Texas
Publication of SG11202102246WA publication Critical patent/SG11202102246WA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67144—Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/14—Details relating to CAD techniques related to nanotechnology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2113/00—Details relating to the application field
    • G06F2113/18—Chip packaging
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H01L2225/06544—Design considerations for via connections, e.g. geometry or layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
SG11202102246WA 2018-09-06 2019-09-06 Nanofabrication and design techniques for 3d ics and configurable asics SG11202102246WA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201862727886P 2018-09-06 2018-09-06
US201962884524P 2019-08-08 2019-08-08
PCT/US2019/049875 WO2020051410A1 (en) 2018-09-06 2019-09-06 Nanofabrication and design techniques for 3d ics and configurable asics

Publications (1)

Publication Number Publication Date
SG11202102246WA true SG11202102246WA (en) 2021-04-29

Family

ID=69723285

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202102246WA SG11202102246WA (en) 2018-09-06 2019-09-06 Nanofabrication and design techniques for 3d ics and configurable asics

Country Status (8)

Country Link
US (4) US12079557B2 (en)
EP (1) EP3847697A4 (en)
JP (1) JP2021536678A (en)
KR (1) KR20210069052A (en)
CN (1) CN112970107A (en)
SG (1) SG11202102246WA (en)
TW (1) TW202025241A (en)
WO (1) WO2020051410A1 (en)

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CN115443525A (en) * 2019-12-17 2022-12-06 库力索法荷兰有限公司 Adhesive tape for receiving discrete components
US11539529B2 (en) * 2020-05-27 2022-12-27 Wipro Limited System and method for facilitating of an internet of things infrastructure for an application
TWI748599B (en) * 2020-08-14 2021-12-01 矽品精密工業股份有限公司 Matching chips system and method of matching chips
EP4409636A1 (en) * 2021-09-30 2024-08-07 Board of Regents, The University of Texas System Tool and processes for pick-and-place assembly
KR20240132491A (en) * 2022-01-14 2024-09-03 보드 오브 리전츠, 더 유니버시티 오브 텍사스 시스템 High-precision heterogeneous integration
WO2023179498A1 (en) * 2022-03-25 2023-09-28 Mediatek Inc. Action masks for macro placement based on density map calculations
CN117316837B (en) * 2023-11-29 2024-03-08 武汉大学 Hybrid bonding continuity simulation model establishment method, system and equipment

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US6784023B2 (en) 1996-05-20 2004-08-31 Micron Technology, Inc. Method of fabrication of stacked semiconductor devices
DE19924935C1 (en) * 1999-05-31 2000-11-30 Fraunhofer Ges Forschung Process for the production of three-dimensional circuits
US6955976B2 (en) * 2002-02-01 2005-10-18 Hewlett-Packard Development Company, L.P. Method for dicing wafer stacks to provide access to interior structures
US7069523B2 (en) * 2002-12-13 2006-06-27 Lsi Logic Corporation Automated selection and placement of memory during design of an integrated circuit
US7262597B2 (en) * 2003-09-15 2007-08-28 Neocera, Llc Hybrid squid microscope with magnetic flux-guide for high resolution magnetic and current imaging by direct magnetic field sensing
DE102004027489B4 (en) * 2004-06-04 2017-03-02 Infineon Technologies Ag A method of arranging chips of a first substrate on a second substrate
EP2132782B1 (en) 2007-02-15 2012-07-11 Transform Solar Pty Ltd. A substrate assembly, an assembly process, and an assembly apparatus
US8585915B2 (en) * 2007-10-29 2013-11-19 Micron Technology, Inc. Methods for fabricating sub-resolution alignment marks on semiconductor structures
US20090127686A1 (en) * 2007-11-21 2009-05-21 Advanced Chip Engineering Technology Inc. Stacking die package structure for semiconductor devices and method of the same
US9922967B2 (en) * 2010-12-08 2018-03-20 Skorpios Technologies, Inc. Multilevel template assisted wafer bonding
KR102111742B1 (en) * 2014-01-14 2020-05-15 삼성전자주식회사 Stacked semiconductor package
US9875536B2 (en) * 2015-03-31 2018-01-23 Kla-Tencor Corp. Sub-pixel and sub-resolution localization of defects on patterned wafers
JP6546783B2 (en) 2015-05-21 2019-07-17 東京応化工業株式会社 Method of manufacturing laminate and method of separating support
JP6663104B2 (en) * 2015-09-10 2020-03-11 富士通株式会社 Semiconductor device and method of controlling semiconductor device
US10109616B2 (en) * 2016-12-22 2018-10-23 Intel Corporation High bandwidth, low profile multi-die package
EP3558600A4 (en) * 2016-12-23 2020-11-25 Board of Regents, The University of Texas System Heterogeneous integration of components onto compact devices using moire based metrology and vacuum based pick-and-place

Also Published As

Publication number Publication date
US20230118578A1 (en) 2023-04-20
US20230124676A1 (en) 2023-04-20
US12079557B2 (en) 2024-09-03
CN112970107A (en) 2021-06-15
TW202025241A (en) 2020-07-01
US20230419010A1 (en) 2023-12-28
JP2021536678A (en) 2021-12-27
US20210350061A1 (en) 2021-11-11
EP3847697A1 (en) 2021-07-14
KR20210069052A (en) 2021-06-10
EP3847697A4 (en) 2022-10-26
WO2020051410A1 (en) 2020-03-12

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