SG11202008449WA - Process for fabricating a donor substrate for the production of a three-dimensional integrated structure and process for fabricating such an integrated structure - Google Patents

Process for fabricating a donor substrate for the production of a three-dimensional integrated structure and process for fabricating such an integrated structure

Info

Publication number
SG11202008449WA
SG11202008449WA SG11202008449WA SG11202008449WA SG11202008449WA SG 11202008449W A SG11202008449W A SG 11202008449WA SG 11202008449W A SG11202008449W A SG 11202008449WA SG 11202008449W A SG11202008449W A SG 11202008449WA SG 11202008449W A SG11202008449W A SG 11202008449WA
Authority
SG
Singapore
Prior art keywords
fabricating
integrated structure
production
donor substrate
dimensional
Prior art date
Application number
SG11202008449WA
Inventor
Gweltaz Gaudin
Didier Landru
Bruno Ghyselen
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Publication of SG11202008449WA publication Critical patent/SG11202008449WA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
SG11202008449WA 2018-03-29 2019-03-22 Process for fabricating a donor substrate for the production of a three-dimensional integrated structure and process for fabricating such an integrated structure SG11202008449WA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1852751A FR3079659B1 (en) 2018-03-29 2018-03-29 METHOD FOR MANUFACTURING A DONOR SUBSTRATE FOR THE PRODUCTION OF AN INTEGRATED THREE-DIMENSIONAL STRUCTURE AND METHOD FOR MANUFACTURING SUCH AN INTEGRATED STRUCTURE
PCT/FR2019/050653 WO2019186035A1 (en) 2018-03-29 2019-03-22 Method for producing a donor substrate for creating a three-dimensional integrated structure, and method for producing such an integrated structure

Publications (1)

Publication Number Publication Date
SG11202008449WA true SG11202008449WA (en) 2020-10-29

Family

ID=62751070

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202008449WA SG11202008449WA (en) 2018-03-29 2019-03-22 Process for fabricating a donor substrate for the production of a three-dimensional integrated structure and process for fabricating such an integrated structure

Country Status (9)

Country Link
US (1) US11239108B2 (en)
EP (1) EP3776642B1 (en)
JP (1) JP7332618B2 (en)
KR (1) KR102703373B1 (en)
CN (1) CN111868915B (en)
FR (1) FR3079659B1 (en)
SG (1) SG11202008449WA (en)
TW (1) TWI846688B (en)
WO (1) WO2019186035A1 (en)

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2809867B1 (en) * 2000-05-30 2003-10-24 Commissariat Energie Atomique FRAGILE SUBSTRATE AND METHOD FOR MANUFACTURING SUCH SUBSTRATE
FR2839199B1 (en) * 2002-04-30 2005-06-24 Soitec Silicon On Insulator METHOD FOR MANUFACTURING SUBSTRATES WITH DETACHMENT OF A TEMPORARY SUPPORT, AND ASSOCIATED SUBSTRATE
FR2857983B1 (en) * 2003-07-24 2005-09-02 Soitec Silicon On Insulator PROCESS FOR PRODUCING AN EPITAXIC LAYER
FR2910702B1 (en) * 2006-12-26 2009-04-03 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A MIXED SUBSTRATE
FR2912259B1 (en) * 2007-02-01 2009-06-05 Soitec Silicon On Insulator PROCESS FOR PRODUCING A SUBSTRATE OF THE "SILICON ON INSULATION" TYPE
FR2922360A1 (en) * 2007-10-12 2009-04-17 Soitec Silicon On Insulator METHOD FOR MANUFACTURING SEMICONDUCTOR TYPE SUBSTRATE ON INTEGRATED GROUND PLAN INSULATOR.
FR2926925B1 (en) * 2008-01-29 2010-06-25 Soitec Silicon On Insulator PROCESS FOR PRODUCING HETEROSTRUCTURES
JP2012023117A (en) * 2010-07-13 2012-02-02 Bridgestone Corp Method for manufacturing intermediate stamper and method for forming uneven pattern
TWI573198B (en) * 2011-09-27 2017-03-01 索泰克公司 Methods of transferring layers of material in 3d integration processes and related structures and devices
FR2980916B1 (en) * 2011-10-03 2014-03-28 Soitec Silicon On Insulator PROCESS FOR PRODUCING A SILICON TYPE STRUCTURE ON INSULATION
FR2983342B1 (en) * 2011-11-30 2016-05-20 Soitec Silicon On Insulator METHOD FOR MANUFACTURING A HETEROSTRUCTURE LIMITING THE DEFECT FORMATION AND HETEROSTRUCTURE THUS OBTAINED
FR3007576B1 (en) * 2013-06-19 2015-07-10 Soitec Silicon On Insulator METHOD OF TRANSFERRING A LAYER OF CIRCUITS.
FR3008543B1 (en) * 2013-07-15 2015-07-17 Soitec Silicon On Insulator METHOD OF LOCATING DEVICES
FR3029538B1 (en) 2014-12-04 2019-04-26 Soitec LAYER TRANSFER METHOD
FR3039003B1 (en) * 2015-07-17 2017-07-28 Soitec Silicon On Insulator PROCESS FOR PRODUCING A SUBSTRATE
EP3144958B1 (en) * 2015-09-17 2021-03-17 Soitec Structure for radiofrequency applications and process for manufacturing such a structure

Also Published As

Publication number Publication date
TWI846688B (en) 2024-07-01
FR3079659A1 (en) 2019-10-04
US11239108B2 (en) 2022-02-01
WO2019186035A1 (en) 2019-10-03
KR102703373B1 (en) 2024-09-06
US20210057268A1 (en) 2021-02-25
CN111868915B (en) 2024-07-23
KR20200136910A (en) 2020-12-08
FR3079659B1 (en) 2020-03-13
JP2021520062A (en) 2021-08-12
EP3776642B1 (en) 2022-05-11
CN111868915A (en) 2020-10-30
EP3776642A1 (en) 2021-02-17
JP7332618B2 (en) 2023-08-23
TW202004991A (en) 2020-01-16

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