SG11202007980UA - Comparator circuit arrangement and method of forming the same - Google Patents
Comparator circuit arrangement and method of forming the sameInfo
- Publication number
- SG11202007980UA SG11202007980UA SG11202007980UA SG11202007980UA SG11202007980UA SG 11202007980U A SG11202007980U A SG 11202007980UA SG 11202007980U A SG11202007980U A SG 11202007980UA SG 11202007980U A SG11202007980U A SG 11202007980UA SG 11202007980U A SG11202007980U A SG 11202007980UA
- Authority
- SG
- Singapore
- Prior art keywords
- forming
- same
- circuit arrangement
- comparator circuit
- comparator
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
- H03K5/2481—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors with at least one differential stage
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00293—Output pulse is a delayed pulse issued after a rising or a falling edge, the length of the output pulse not being in relation with the length of the input triggering pulse
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SG10201802382Y | 2018-03-22 | ||
| PCT/SG2019/050133 WO2019182511A1 (en) | 2018-03-22 | 2019-03-11 | Comparator circuit arrangement and method of forming the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG11202007980UA true SG11202007980UA (en) | 2020-09-29 |
Family
ID=67988079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG11202007980UA SG11202007980UA (en) | 2018-03-22 | 2019-03-11 | Comparator circuit arrangement and method of forming the same |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US11108386B2 (en) |
| SG (1) | SG11202007980UA (en) |
| WO (1) | WO2019182511A1 (en) |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3970919A (en) | 1975-06-19 | 1976-07-20 | The United States Of America As Represented By The Secretary Of The Air Force | Regulating digital power supply |
| JPH07104014A (en) * | 1993-10-04 | 1995-04-21 | Sanyo Electric Co Ltd | Comparator circuit |
| US20080143697A1 (en) * | 2006-12-13 | 2008-06-19 | Tomokazu Kojima | Drive voltage control device |
| US7570190B1 (en) * | 2008-03-28 | 2009-08-04 | Motorola, Inc. | Method and system for operating a comparator |
| CN202906862U (en) * | 2012-11-09 | 2013-04-24 | 苏州海格新能源汽车电控系统科技有限公司 | A vehicle rotating speed signal analyzing circuit |
| JP6360560B2 (en) * | 2013-09-09 | 2018-07-18 | テキサス インスツルメンツ インコーポレイテッド | Intrinsic comparator delay for output clamping circuit |
| JP6180318B2 (en) * | 2013-12-27 | 2017-08-16 | ソニーセミコンダクタソリューションズ株式会社 | Comparator circuit |
| US10021331B2 (en) * | 2014-07-14 | 2018-07-10 | Sony Corporation | Comparator, AD converter, solid-state imaging device, electronic apparatus, and method of controlling comparator |
| US9602088B1 (en) * | 2015-09-11 | 2017-03-21 | Texas Instruments Incorporated | Ultra-low power comparator with sampling control loop adjusting frequency and/or sample aperture window |
-
2019
- 2019-03-11 SG SG11202007980UA patent/SG11202007980UA/en unknown
- 2019-03-11 US US16/971,226 patent/US11108386B2/en active Active
- 2019-03-11 WO PCT/SG2019/050133 patent/WO2019182511A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| US20210119623A1 (en) | 2021-04-22 |
| US11108386B2 (en) | 2021-08-31 |
| WO2019182511A1 (en) | 2019-09-26 |
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