SG11201910710VA - Silicon-on-insulator with porous silicon substrate - Google Patents

Silicon-on-insulator with porous silicon substrate

Info

Publication number
SG11201910710VA
SG11201910710VA SG11201910710VA SG11201910710VA SG11201910710VA SG 11201910710V A SG11201910710V A SG 11201910710VA SG 11201910710V A SG11201910710V A SG 11201910710VA SG 11201910710V A SG11201910710V A SG 11201910710VA SG 11201910710V A SG11201910710V A SG 11201910710VA
Authority
SG
Singapore
Prior art keywords
silicon
insulator
porous
silicon substrate
substrate
Prior art date
Application number
SG11201910710VA
Inventor
Stephen Alan Fanelli
Richard Hammond
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of SG11201910710VA publication Critical patent/SG11201910710VA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642Isolation within the component, i.e. internal isolation
    • H01L29/0649Dielectric regions, e.g. SiO2 regions, air gaps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002Preparing wafers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3063Electrolytic etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
SG11201910710VA 2017-06-30 2018-04-23 Silicon-on-insulator with porous silicon substrate SG11201910710VA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/638,874 US10134837B1 (en) 2017-06-30 2017-06-30 Porous silicon post processing
PCT/US2018/028912 WO2019005271A1 (en) 2017-06-30 2018-04-23 Silicon-on-insulator with porous silicon substrate

Publications (1)

Publication Number Publication Date
SG11201910710VA true SG11201910710VA (en) 2020-01-30

Family

ID=62117124

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201910710VA SG11201910710VA (en) 2017-06-30 2018-04-23 Silicon-on-insulator with porous silicon substrate

Country Status (6)

Country Link
US (1) US10134837B1 (en)
EP (1) EP3646370B1 (en)
CN (1) CN110800088A (en)
SG (1) SG11201910710VA (en)
TW (1) TW201917884A (en)
WO (1) WO2019005271A1 (en)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10109550B2 (en) 2016-08-12 2018-10-23 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10784233B2 (en) 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US20200235040A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US20200235066A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US20200235074A1 (en) * 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
WO2020153983A1 (en) 2019-01-23 2020-07-30 Qorvo Us, Inc. Rf semiconductor device and manufacturing method thereof
US11387157B2 (en) * 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
FR3103631B1 (en) 2019-11-25 2022-09-09 Commissariat Energie Atomique INTEGRATED ELECTRONIC DEVICE COMPRISING A COIL AND METHOD FOR MANUFACTURING SUCH A DEVICE
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
CN113173861B (en) * 2021-06-11 2021-09-14 长春市吉达自动化系统有限公司 Automatic system and method for lysine production crystallization extraction

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2602597B2 (en) 1991-12-27 1997-04-23 信越半導体株式会社 Method for manufacturing thin film SOI substrate
WO1996015550A1 (en) 1994-11-10 1996-05-23 Lawrence Semiconductor Research Laboratory, Inc. Silicon-germanium-carbon compositions and processes thereof
US6407441B1 (en) 1997-12-29 2002-06-18 Texas Instruments Incorporated Integrated circuit and method of using porous silicon to achieve component isolation in radio frequency applications
GB9907184D0 (en) * 1999-03-30 1999-05-26 Philips Electronics Nv A method of manufacturing a semiconductor device
US7084046B2 (en) * 2001-11-29 2006-08-01 Shin-Etsu Handotai Co., Ltd. Method of fabricating SOI wafer
EP1437764A1 (en) * 2003-01-10 2004-07-14 S.O.I. Tec Silicon on Insulator Technologies S.A. A compliant substrate for a heteroepitaxy, a heteroepitaxial structure and a method for fabricating a compliant substrate
US20040245571A1 (en) 2003-02-13 2004-12-09 Zhiyuan Cheng Semiconductor-on-insulator article and method of making same
US7811382B2 (en) * 2006-05-30 2010-10-12 Freescale Semiconductor, Inc. Method for forming a semiconductor structure having a strained silicon layer
US20090124038A1 (en) * 2007-11-14 2009-05-14 Mark Ewing Tuttle Imager device, camera, and method of manufacturing a back side illuminated imager
US7767546B1 (en) * 2009-01-12 2010-08-03 International Business Machines Corporation Low cost fabrication of double box back gate silicon-on-insulator wafers with built-in shallow trench isolation in back gate layer
US8395191B2 (en) * 2009-10-12 2013-03-12 Monolithic 3D Inc. Semiconductor device and structure
US8362482B2 (en) * 2009-04-14 2013-01-29 Monolithic 3D Inc. Semiconductor device and structure
US8471340B2 (en) 2009-11-30 2013-06-25 International Business Machines Corporation Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure
US8536021B2 (en) 2010-12-24 2013-09-17 Io Semiconductor, Inc. Trap rich layer formation techniques for semiconductor devices
US8809156B1 (en) * 2013-01-25 2014-08-19 International Business Machines Corporation Method for implementing deep trench enabled high current capable bipolar transistor for current switching and output driver applications
US8927338B1 (en) * 2013-06-13 2015-01-06 International Business Machines Corporation Flexible, stretchable electronic devices
FR3024587B1 (en) * 2014-08-01 2018-01-26 Soitec METHOD FOR MANUFACTURING HIGHLY RESISTIVE STRUCTURE
US10312134B2 (en) 2014-09-04 2019-06-04 Globalwafers Co., Ltd. High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss
US10181428B2 (en) * 2015-08-28 2019-01-15 Skyworks Solutions, Inc. Silicon on porous silicon
US20180068886A1 (en) 2016-09-02 2018-03-08 Qualcomm Incorporated Porous semiconductor layer transfer for an integrated circuit structure

Also Published As

Publication number Publication date
TW201917884A (en) 2019-05-01
CN110800088A (en) 2020-02-14
WO2019005271A1 (en) 2019-01-03
US10134837B1 (en) 2018-11-20
EP3646370A1 (en) 2020-05-06
EP3646370B1 (en) 2023-12-13

Similar Documents

Publication Publication Date Title
SG11201910710VA (en) Silicon-on-insulator with porous silicon substrate
HK1257850A1 (en) Leaflet support devices
EP3477691A4 (en) Holding device
EP3337935A4 (en) Self-sealing articles including elastic porous layer
EP3494314A4 (en) Fixing device
AU201812705S (en) Glass
SG11201913717RA (en) Substrate holding device
GB201713629D0 (en) Surface microstructures
EP3339851A4 (en) Silicon substrate analyzing device
GB201701387D0 (en) Glass substrate pick up and place device
SG10202009031VA (en) Intra-mould substrate
EP3437808A4 (en) Muscle-power support device
EP3467348A4 (en) Support device
EP3437809A4 (en) Muscle-power support device
HUE057728T2 (en) Substrate support
EP3506728A4 (en) Mounting device
EP3482415A4 (en) Substrate carrier
GB201315727D0 (en) Coated silicon wafer
EP3509115A4 (en) Photovoltaic device
EP3560407A4 (en) Substrate attaching structure
FI20175587A (en) Silicon-on-insulator with crystalline silicon oxide
GB2552508B (en) Substrate
EP3557966A4 (en) Substrate transfer device
GB201715449D0 (en) Porous hierarchical substrate
EP3722017A4 (en) Holding device