SG11201805819RA - Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory - Google Patents
Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memoryInfo
- Publication number
- SG11201805819RA SG11201805819RA SG11201805819RA SG11201805819RA SG11201805819RA SG 11201805819R A SG11201805819R A SG 11201805819RA SG 11201805819R A SG11201805819R A SG 11201805819RA SG 11201805819R A SG11201805819R A SG 11201805819RA SG 11201805819R A SG11201805819R A SG 11201805819RA
- Authority
- SG
- Singapore
- Prior art keywords
- california
- international
- memory
- apparatuses
- data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1045—Read-write mode select circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Abstract
INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property -, Organization MD 1101111 0 11101 010 11111 HO 11111 0 MOH 0111 100 11111 0111 00 111110 ill OEN International Bureau ... .... ..Yjd ..... ...,/ (10) International Publication Number (43) International Publication Date WO 2017/123413 Al 20 July 2017 (20.07.2017) WIPO I PCT (51) International Patent Classification: (81) Designated States (unless otherwise indicated, for every G06F 12/02 (2006.01) GO6F 3/06 (2006.01) kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, (21) International Application Number: BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, PCT/US2016/068834 DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, (22) International Filing Date: HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, 28 December 2016 (28.12.2016) KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, (25) Filing Language: English NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, (26) Publication Language: English RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, (30) Priority Data: ZA, ZM, ZW. 14/992,979 11 January 2016 (11.01.2016) US (84) Designated States (unless otherwise indicated, for every (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; kind of regional protection available): ARIPO (BW, GH, 8000 South Federal Way, Boise, Idaho 83716 (US). GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, (72) Inventors: SUNDARAM, Rajesh; 1007 Kirby Court, Fol- TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, som, California 95630 (US). KAU, Derchang; 10847 Linda Vista Drive, Cupertino, California 95014 (US). DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, JUNGROTH, Owen W.; 17550 Uplands Drive, Sonora, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, California 95370 (US). CHU, Daniel; 109 Triff Court, Fol- — som, California 95630 (US). ZENG, Raymond W.; 585 GW, KM, ML, MR, NE, SN, TD, TG). Worley Avenue, Sunnyvale, California 94085 (US). Published: = QAWAMI, Shekoufeh; 2520 Stratford Circle, EL Dorado — with international search report (Art. 21(3)) Hills, California 95762 (US). = (74) Agents: ENG, Kimton et al.; Dorsey & Whitney LLP, 701 5th Ave, Suite 6100, Seattle, Washington 98104 (US). = (54) Title: APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING MULTIPLE PARTITIONS OF A NON- - VOLATILE MEMORY = r360 = — Data UO 2 66 CommandlAddres9 Interface Interface ,e-300 364 Data Block -)' CommandUl Block ( - 380 = = Conlrn and/Address Bus 374(0) -‘ LCO LC1 -\ -374(1) LC N --, 374(N) = — Pilo arn 0 372(0) Partition 1 372(1) Patton N 372(N) 390376{0) Data Buffer Data Buffer Data Buffer 0) 376(1) 11 Data Bus M FIG.3 1-1 71. M \" (57) : Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are dis - I-1 ---- closed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions, each may include IN a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to © independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command ei responsive to receiving the respective memory access command. The example apparatus may further include a controller configured 0 to receive the plurality of memory access commands and determine a respective target partition for each of the plurality of memory ,1 . access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/992,979 US10719237B2 (en) | 2016-01-11 | 2016-01-11 | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory |
PCT/US2016/068834 WO2017123413A1 (en) | 2016-01-11 | 2016-12-28 | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11201805819RA true SG11201805819RA (en) | 2018-08-30 |
Family
ID=59275818
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11201805819RA SG11201805819RA (en) | 2016-01-11 | 2016-12-28 | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory |
Country Status (8)
Country | Link |
---|---|
US (3) | US10719237B2 (en) |
EP (1) | EP3403184B1 (en) |
JP (2) | JP6918805B2 (en) |
KR (1) | KR102152281B1 (en) |
CN (1) | CN108701081B (en) |
SG (1) | SG11201805819RA (en) |
TW (1) | TWI629686B (en) |
WO (1) | WO2017123413A1 (en) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10719237B2 (en) | 2016-01-11 | 2020-07-21 | Micron Technology, Inc. | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory |
US10509592B1 (en) | 2016-07-26 | 2019-12-17 | Pavilion Data Systems, Inc. | Parallel data transfer for solid state drives using queue pair subsets |
US10642741B2 (en) * | 2017-02-06 | 2020-05-05 | International Business Machines Corporation | Accessing tables with heterogeneous partitions |
KR102469958B1 (en) * | 2017-10-27 | 2022-11-25 | 삼성전자주식회사 | Nonvolatile memory device configured to be accessed without block address and method of operating the same |
US11416395B2 (en) | 2018-02-05 | 2022-08-16 | Micron Technology, Inc. | Memory virtualization for accessing heterogeneous memory components |
US20190243787A1 (en) * | 2018-02-05 | 2019-08-08 | Micron Technology, Inc. | Memory Systems having Controllers Embedded in Packages of Integrated Circuit Memory |
US10782908B2 (en) | 2018-02-05 | 2020-09-22 | Micron Technology, Inc. | Predictive data orchestration in multi-tier memory systems |
US20210406410A1 (en) * | 2018-12-21 | 2021-12-30 | Micron Technology, Inc. | Method and device to ensure a secure memory access |
US10852949B2 (en) | 2019-04-15 | 2020-12-01 | Micron Technology, Inc. | Predictive data pre-fetching in a data storage device |
CN112035053A (en) * | 2019-06-04 | 2020-12-04 | 华邦电子股份有限公司 | Memory storage device and operation method thereof |
DE102019213998A1 (en) * | 2019-09-13 | 2021-03-18 | Airbus Defence and Space GmbH | PROCESSOR SYSTEM WITH MEMORY INTERLOCATION AND ACCESS METHODS TO MEMORY-INTERLOCATED MEMORY BANKS |
JP2021174565A (en) | 2020-04-24 | 2021-11-01 | キオクシア株式会社 | Semiconductor storage device |
US11137920B1 (en) * | 2020-04-30 | 2021-10-05 | Micron Technology, Inc. | Storing zones in a zone namespace on separate planes of a multi-plane memory device |
TWI743859B (en) * | 2020-06-30 | 2021-10-21 | 旺宏電子股份有限公司 | Memory device, electronic device, and associated read method |
CN114816652A (en) * | 2021-01-29 | 2022-07-29 | 上海阵量智能科技有限公司 | Command processing device and method, electronic device, and computer storage medium |
DE102021107044A1 (en) | 2021-03-10 | 2022-09-15 | Elmos Semiconductor Se | Safety-relevant computer system with a data memory and a data memory |
US11461366B1 (en) | 2021-10-20 | 2022-10-04 | Bnsf Railway Company | System and method for data pruning via dynamic partition management |
CN115454330A (en) * | 2022-08-03 | 2022-12-09 | 中勍科技股份有限公司 | Method for managing multiple SSD reads and writes in parallel |
Family Cites Families (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5822251A (en) * | 1997-08-25 | 1998-10-13 | Bit Microsystems, Inc. | Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers |
US6707743B2 (en) * | 1998-10-01 | 2004-03-16 | Monolithic System Technology, Inc. | Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division |
US7827348B2 (en) * | 2000-01-06 | 2010-11-02 | Super Talent Electronics, Inc. | High performance flash memory devices (FMD) |
US6553472B2 (en) * | 2001-01-12 | 2003-04-22 | Sun Microsystems, Inc. | Method for programming clock delays, command delays, read command parameter delays, and write command parameter delays of a memory controller in a high performance microprocessor |
US7500075B1 (en) * | 2001-04-17 | 2009-03-03 | Rambus Inc. | Mechanism for enabling full data bus utilization without increasing data granularity |
JP4256600B2 (en) | 2001-06-19 | 2009-04-22 | Tdk株式会社 | MEMORY CONTROLLER, FLASH MEMORY SYSTEM PROVIDED WITH MEMORY CONTROLLER, AND FLASH MEMORY CONTROL METHOD |
ITRM20010529A1 (en) | 2001-08-31 | 2003-02-28 | Micron Technology Inc | COMMAND USER INTERFACE FOR MULTIPLE BREAKDOWN MEMORY. |
US6678204B2 (en) * | 2001-12-27 | 2004-01-13 | Elpida Memory Inc. | Semiconductor memory device with high-speed operation and methods of using and designing thereof |
ITTO20021035A1 (en) | 2002-11-29 | 2004-05-30 | St Microelectronics Srl | NON VOLATILE MEMORY DEVICE FOR READING AND SIMULATING WRITING. |
US8233322B2 (en) | 2003-10-10 | 2012-07-31 | Micron Technology, Inc. | Multi-partition memory with separated read and algorithm datalines |
US7519788B2 (en) * | 2004-06-04 | 2009-04-14 | Micron Technology, Inc. | System and method for an asynchronous data buffer having buffer write and read pointers |
US7464225B2 (en) * | 2005-09-26 | 2008-12-09 | Rambus Inc. | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology |
TWI543185B (en) | 2005-09-30 | 2016-07-21 | 考文森智財管理公司 | Memory with output control and system thereof |
US7447848B2 (en) * | 2006-01-04 | 2008-11-04 | Barry Wagner | Memory device row and/or column access efficiency |
US7701764B2 (en) * | 2006-05-17 | 2010-04-20 | Micron Technology, Inc. | Apparatus and method for reduced peak power consumption during common operation of multi-NAND flash memory devices |
US8935302B2 (en) | 2006-12-06 | 2015-01-13 | Intelligent Intellectual Property Holdings 2 Llc | Apparatus, system, and method for data block usage information synchronization for a non-volatile storage volume |
JP5103663B2 (en) * | 2007-09-27 | 2012-12-19 | ルネサスエレクトロニクス株式会社 | Memory control device |
US7782703B2 (en) * | 2008-02-01 | 2010-08-24 | Qimonda North America Corp. | Semiconductor memory having a bank with sub-banks |
JP5317657B2 (en) | 2008-12-04 | 2013-10-16 | 三洋電機株式会社 | Image display device |
JP5420648B2 (en) | 2009-05-22 | 2014-02-19 | 株式会社日立製作所 | Semiconductor device |
US20100318720A1 (en) | 2009-06-16 | 2010-12-16 | Saranyan Rajagopalan | Multi-Bank Non-Volatile Memory System with Satellite File System |
US8447908B2 (en) * | 2009-09-07 | 2013-05-21 | Bitmicro Networks, Inc. | Multilevel memory bus system for solid-state mass storage |
US8543758B2 (en) * | 2011-05-31 | 2013-09-24 | Micron Technology, Inc. | Apparatus including memory channel control circuit and related methods for relaying commands to logical units |
US8700879B2 (en) | 2011-08-31 | 2014-04-15 | Micron Technology, Inc. | Concurrent memory operations |
US8593866B2 (en) * | 2011-11-11 | 2013-11-26 | Sandisk Technologies Inc. | Systems and methods for operating multi-bank nonvolatile memory |
US8699277B2 (en) | 2011-11-16 | 2014-04-15 | Qualcomm Incorporated | Memory configured to provide simultaneous read/write access to multiple banks |
KR101903095B1 (en) | 2011-11-21 | 2018-10-02 | 삼성전자주식회사 | Nonvolatile memory device and oeprating method of controller controlling nonvolailte memory device |
US9396101B2 (en) * | 2012-06-12 | 2016-07-19 | International Business Machines Corporation | Shared physical memory protocol |
CN103176750B (en) * | 2013-02-27 | 2016-01-20 | 武汉虹旭信息技术有限责任公司 | Based on mobile Internet data storage system and the method thereof of staggered time subregion |
JP2014164789A (en) * | 2013-02-27 | 2014-09-08 | Toshiba Corp | Semiconductor memory device |
US20140289446A1 (en) * | 2013-03-21 | 2014-09-25 | Kabushiki Kaisha Toshiba | Memory system and memory |
TWI573148B (en) * | 2013-08-02 | 2017-03-01 | 東芝股份有限公司 | A controller, a memory system, and a memory device |
CN104641418B (en) | 2013-08-19 | 2018-09-28 | 东芝存储器株式会社 | Storage system |
US9293188B2 (en) * | 2014-02-03 | 2016-03-22 | Advanced Micro Devices, Inc. | Memory and memory controller for high reliability operation and method |
CN103942151A (en) * | 2014-04-10 | 2014-07-23 | 深圳市硅格半导体有限公司 | Data storage method and device for flash memory |
US9384831B2 (en) * | 2014-05-29 | 2016-07-05 | Intel Corporation | Cross-point memory single-selection write technique |
TWI554944B (en) * | 2014-06-20 | 2016-10-21 | 慧榮科技股份有限公司 | Flash memory controlling apparatus, flash memory controlling system and flash memory controlling method |
CN104111894A (en) * | 2014-07-17 | 2014-10-22 | 记忆科技(深圳)有限公司 | Method for improving multi-partition sequential read-write performance and system thereof |
US9691452B2 (en) | 2014-08-15 | 2017-06-27 | Micron Technology, Inc. | Apparatuses and methods for concurrently accessing different memory planes of a memory |
US9607672B2 (en) * | 2014-11-14 | 2017-03-28 | Cavium, Inc. | Managing skew in data signals with adjustable strobe |
KR102424702B1 (en) * | 2015-11-19 | 2022-07-25 | 삼성전자주식회사 | Non-volatile memory module and electronic device having the same |
US10719237B2 (en) | 2016-01-11 | 2020-07-21 | Micron Technology, Inc. | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory |
-
2016
- 2016-01-11 US US14/992,979 patent/US10719237B2/en active Active
- 2016-12-28 JP JP2018535296A patent/JP6918805B2/en active Active
- 2016-12-28 CN CN201680081702.4A patent/CN108701081B/en active Active
- 2016-12-28 WO PCT/US2016/068834 patent/WO2017123413A1/en active Application Filing
- 2016-12-28 SG SG11201805819RA patent/SG11201805819RA/en unknown
- 2016-12-28 KR KR1020187023018A patent/KR102152281B1/en active IP Right Grant
- 2016-12-28 EP EP16885432.1A patent/EP3403184B1/en active Active
-
2017
- 2017-01-11 TW TW106100884A patent/TWI629686B/en active
-
2020
- 2020-07-10 US US16/926,431 patent/US11354040B2/en active Active
-
2021
- 2021-07-21 JP JP2021120142A patent/JP7240452B2/en active Active
-
2022
- 2022-05-05 US US17/662,100 patent/US11768603B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US10719237B2 (en) | 2020-07-21 |
US20170199666A1 (en) | 2017-07-13 |
EP3403184A1 (en) | 2018-11-21 |
US11768603B2 (en) | 2023-09-26 |
EP3403184A4 (en) | 2019-09-04 |
JP7240452B2 (en) | 2023-03-15 |
TWI629686B (en) | 2018-07-11 |
KR102152281B1 (en) | 2020-10-27 |
US11354040B2 (en) | 2022-06-07 |
JP2019505910A (en) | 2019-02-28 |
US20220261151A1 (en) | 2022-08-18 |
KR20180094128A (en) | 2018-08-22 |
CN108701081A (en) | 2018-10-23 |
EP3403184B1 (en) | 2023-11-08 |
US20200341635A1 (en) | 2020-10-29 |
CN108701081B (en) | 2022-06-21 |
WO2017123413A1 (en) | 2017-07-20 |
JP6918805B2 (en) | 2021-08-11 |
JP2021168203A (en) | 2021-10-21 |
TW201732830A (en) | 2017-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
SG11201805819RA (en) | Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory | |
SG11201809795VA (en) | Memory access techniques in memory devices with multiple partitions | |
SG11201809343RA (en) | Systems and methods for correcting error in a first classifier by evaluating classifier output in parallel | |
SG11201903631XA (en) | Neural network instruction set architecture | |
SG11201908675PA (en) | Computer-implemented system and method for performing transaction mixing on a blockchain | |
SG11201805071RA (en) | Communications constellation optimisation facility | |
SG11201807848PA (en) | Efficient live-migration of remotely accessed data | |
SG11201907679TA (en) | Business verification method and apparatus | |
SG11201804807VA (en) | Computer architecture and method for modifying data intake parameters based on a predictive model | |
SG11201804841VA (en) | Hardware integrity check | |
SG11201901026VA (en) | Systems and methods for configuring field devices using a configuration device | |
SG11201804541PA (en) | Card handling devices and related assemblies and components | |
SG11201804372PA (en) | Tracking and manipulating cellular rna via nuclear delivery of crispr/cas9 | |
SG11201805281YA (en) | Resource allocation for computer processing | |
SG11201907532VA (en) | Active boundary quilt architecture memory | |
SG11201803790QA (en) | In-situ quantum error correction | |
SG11201907861WA (en) | Variable beam spacing, timing, and power for vehicle sensors | |
SG11201900093VA (en) | Mechanism to accelerate graphics workloads in a multi-core computing architecture | |
SG11201804948UA (en) | Locator diagnostic for emergency dispatch | |
SG11201908238SA (en) | Anti-c5 antibodies and uses thereof | |
SG11201902738PA (en) | Vehicle collision avoidance | |
SG11201407790SA (en) | Methods and systems for gas lift rate management | |
SG11201806067SA (en) | Write-allocation for a cache based on execute permissions | |
SG11201807325UA (en) | Optimizing range of aircraft docking system | |
SG11201908198RA (en) | Flow control for wireless devices |