SG10201900042WA - Storage device storing data in order based on barrier command - Google Patents

Storage device storing data in order based on barrier command

Info

Publication number
SG10201900042WA
SG10201900042WA SG10201900042WA SG10201900042WA SG10201900042WA SG 10201900042W A SG10201900042W A SG 10201900042WA SG 10201900042W A SG10201900042W A SG 10201900042WA SG 10201900042W A SG10201900042W A SG 10201900042WA SG 10201900042W A SG10201900042W A SG 10201900042WA
Authority
SG
Singapore
Prior art keywords
data
programming
storage device
mapping
storing data
Prior art date
Application number
SG10201900042WA
Inventor
Hwang Jooyoung
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201900042WA publication Critical patent/SG10201900042WA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)

Abstract

A method of programming data to a storage device including a nonvolatile memory device includes receiving first to third barrier commands from a host, receiving first to third data corresponding to the first to third barrier commands from the host, merging the first and second barrier commands and programming the first and second data to the nonvolatile memory device sequentially based on an order of the first and second barrier commands, verifying program completion of both the first and second data, mapping in mapping information of the first and second data when the programming of the first and second data is completed, and mapping out the information of both the first and second data when the programming of at least one of the first and second data is not complete, and programming the third data to the nonvolatile memory device after the mapping in or the mapping out. FIG. 1
SG10201900042WA 2018-01-12 2019-01-03 Storage device storing data in order based on barrier command SG10201900042WA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201862616718P 2018-01-12 2018-01-12
KR1020180068127A KR102646724B1 (en) 2018-01-12 2018-06-14 Storage device storing data in order based on barrier command

Publications (1)

Publication Number Publication Date
SG10201900042WA true SG10201900042WA (en) 2019-08-27

Family

ID=67468995

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201900042WA SG10201900042WA (en) 2018-01-12 2019-01-03 Storage device storing data in order based on barrier command

Country Status (2)

Country Link
KR (1) KR102646724B1 (en)
SG (1) SG10201900042WA (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102262209B1 (en) * 2018-02-09 2021-06-09 한양대학교 산학협력단 Method and apparatus for sending barrier command using dummy io request
KR102254501B1 (en) * 2018-10-19 2021-05-21 한양대학교 산학협력단 Partially order preserving i/o scheduler and method thereof
KR102132387B1 (en) * 2018-10-19 2020-07-09 한양대학교 산학협력단 Method and apparatus for logging based on barrier
KR20220023649A (en) 2020-08-21 2022-03-02 에스케이하이닉스 주식회사 Memory controller and operating method thereof
KR20230135346A (en) 2022-03-16 2023-09-25 에스케이하이닉스 주식회사 Memory controller and operating method thereof

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101734199B1 (en) * 2010-12-29 2017-05-24 삼성전자주식회사 Data storage system having multi-bit memory device and operating method thereof
KR101942272B1 (en) * 2011-12-27 2019-01-28 삼성전자주식회사 A method for controlling nonvolatile memory, a nonvolatile memory controller thereof, and a memory system having the same
US9798631B2 (en) * 2014-02-04 2017-10-24 Microsoft Technology Licensing, Llc Block storage by decoupling ordering from durability

Also Published As

Publication number Publication date
KR102646724B1 (en) 2024-03-14
KR20190086341A (en) 2019-07-22

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