SG10201900011WA - Neuromorphic circuit having 3d stacked structure and semiconductor device having the same - Google Patents

Neuromorphic circuit having 3d stacked structure and semiconductor device having the same

Info

Publication number
SG10201900011WA
SG10201900011WA SG10201900011WA SG10201900011WA SG 10201900011W A SG10201900011W A SG 10201900011WA SG 10201900011W A SG10201900011W A SG 10201900011WA SG 10201900011W A SG10201900011W A SG 10201900011WA
Authority
SG
Singapore
Prior art keywords
semiconductor layer
synaptic
semiconductor device
neuromorphic circuit
same
Prior art date
Application number
Inventor
Cho Woo-Yeong
O Seong-Il
Yu Hak-Soo
Choi Min-su
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of SG10201900011WA publication Critical patent/SG10201900011WA/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Biomedical Technology (AREA)
  • Health & Medical Sciences (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biophysics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Artificial Intelligence (AREA)
  • Evolutionary Computation (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Computing Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Computational Linguistics (AREA)
  • Neurology (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer. FIG. 1
SG10201900011W 2018-04-17 2019-01-02 Neuromorphic circuit having 3d stacked structure and semiconductor device having the same SG10201900011WA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020180044534A KR102589968B1 (en) 2018-04-17 2018-04-17 Neuromorphic circuit having 3D stacked structure and Semiconductor device having the same

Publications (1)

Publication Number Publication Date
SG10201900011WA true SG10201900011WA (en) 2019-11-28

Family

ID=64744475

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201900011W SG10201900011WA (en) 2018-04-17 2019-01-02 Neuromorphic circuit having 3d stacked structure and semiconductor device having the same

Country Status (5)

Country Link
US (1) US11410026B2 (en)
EP (1) EP3557488A1 (en)
KR (1) KR102589968B1 (en)
CN (1) CN110390388A (en)
SG (1) SG10201900011WA (en)

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KR102607860B1 (en) * 2018-05-16 2023-11-29 삼성전자주식회사 Neuromorphic apparatus having 3d stacked synaptic structure and memory apparatus having the same
US11604971B2 (en) * 2018-05-16 2023-03-14 Samsung Electronics Co., Ltd. Neuromorphic apparatus having 3D stacked synaptic structure and memory device having the same
EP3928319A4 (en) 2019-02-22 2022-11-30 Micron Technology, Inc. Memory device interface and method
WO2021133826A1 (en) * 2019-12-27 2021-07-01 Micron Technology, Inc. Neuromorphic memory device and method
US11635910B2 (en) 2019-12-30 2023-04-25 Micron Technology, Inc. Memory device interface and method
CN114902332A (en) 2019-12-31 2022-08-12 美光科技公司 Memory module multiport buffering technique
US11887647B2 (en) 2020-04-09 2024-01-30 Micron Technology, Inc. Deep learning accelerator and random access memory with separate memory access connections
US11874897B2 (en) 2020-04-09 2024-01-16 Micron Technology, Inc. Integrated circuit device with deep learning accelerator and random access memory
US11355175B2 (en) 2020-04-09 2022-06-07 Micron Technology, Inc. Deep learning accelerator and random access memory with a camera interface
WO2021205941A1 (en) * 2020-04-09 2021-10-14 国立研究開発法人科学技術振興機構 Three-dimensional array device
US11461651B2 (en) * 2020-04-09 2022-10-04 Micron Technology, Inc. System on a chip with deep learning accelerator and random access memory
US11397885B2 (en) 2020-04-29 2022-07-26 Sandisk Technologies Llc Vertical mapping and computing for deep neural networks in non-volatile memory
US20240038726A1 (en) * 2021-02-10 2024-02-01 Panasonic Intellectual Property Management Co., Ltd. Ai module
KR102507461B1 (en) * 2021-02-16 2023-03-07 고려대학교 산학협력단 In-memory accelerator for layer-wise quantized neural networks and operation method thereof
KR102554519B1 (en) * 2021-06-24 2023-07-12 한양대학교 산학협력단 3d neuromorphic system and operating method thereof

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US8510244B2 (en) 2009-03-20 2013-08-13 ISC8 Inc. Apparatus comprising artificial neuronal assembly
FR2968808A1 (en) 2010-12-08 2012-06-15 Commissariat Energie Atomique ELECTRONIC CIRCUIT WITH NEUROMORPHIC ARCHITECTURE
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CN103946981B (en) 2011-12-02 2016-11-09 英特尔公司 There is the stacked storage of the interface providing skew interconnection
US8996430B2 (en) 2012-01-27 2015-03-31 International Business Machines Corporation Hierarchical scalable neuromorphic synaptronic system for synaptic and structural plasticity
US8977578B1 (en) 2012-06-27 2015-03-10 Hrl Laboratories, Llc Synaptic time multiplexing neuromorphic network that forms subsets of connections during different time slots
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Also Published As

Publication number Publication date
CN110390388A (en) 2019-10-29
US11410026B2 (en) 2022-08-09
KR102589968B1 (en) 2023-10-16
KR20190121048A (en) 2019-10-25
EP3557488A1 (en) 2019-10-23
US20190318230A1 (en) 2019-10-17

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