SG10201808256PA - Method and system for dynamically detecting, analyzing, monitoring, investigating and/or executing a live target program - Google Patents

Method and system for dynamically detecting, analyzing, monitoring, investigating and/or executing a live target program

Info

Publication number
SG10201808256PA
SG10201808256PA SG10201808256PA SG10201808256PA SG10201808256PA SG 10201808256P A SG10201808256P A SG 10201808256PA SG 10201808256P A SG10201808256P A SG 10201808256PA SG 10201808256P A SG10201808256P A SG 10201808256PA SG 10201808256P A SG10201808256P A SG 10201808256PA
Authority
SG
Singapore
Prior art keywords
investigating
analyzing
executing
monitoring
target program
Prior art date
Application number
SG10201808256PA
Inventor
Xuhua Ding
Jiaqi Hong
Original Assignee
Singapore Management Univ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Singapore Management Univ filed Critical Singapore Management Univ
Priority to SG10201808256PA priority Critical patent/SG10201808256PA/en
Priority to PCT/SG2019/050372 priority patent/WO2020060481A1/en
Publication of SG10201808256PA publication Critical patent/SG10201808256PA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
    • G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/109—Address translation for multiple virtual address spaces, e.g. segmentation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1458—Protection against unauthorised use of memory or access to memory by checking the subject access rights
    • G06F12/1491—Protection against unauthorised use of memory or access to memory by checking the subject access rights in a hierarchical protection system, e.g. privilege levels, memory rings
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1052—Security improvement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1056—Simplification
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/15—Use in a specific computing environment
    • G06F2212/151—Emulated environment, e.g. virtual machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/651—Multi-level translation tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Storage Device Security (AREA)
SG10201808256PA 2018-09-21 2018-09-21 Method and system for dynamically detecting, analyzing, monitoring, investigating and/or executing a live target program SG10201808256PA (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
SG10201808256PA SG10201808256PA (en) 2018-09-21 2018-09-21 Method and system for dynamically detecting, analyzing, monitoring, investigating and/or executing a live target program
PCT/SG2019/050372 WO2020060481A1 (en) 2018-09-21 2019-07-29 Method and system for dynamically detecting, analyzing, monitoring, investigating and/or executing a live target program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SG10201808256PA SG10201808256PA (en) 2018-09-21 2018-09-21 Method and system for dynamically detecting, analyzing, monitoring, investigating and/or executing a live target program

Publications (1)

Publication Number Publication Date
SG10201808256PA true SG10201808256PA (en) 2020-04-29

Family

ID=69888960

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201808256PA SG10201808256PA (en) 2018-09-21 2018-09-21 Method and system for dynamically detecting, analyzing, monitoring, investigating and/or executing a live target program

Country Status (2)

Country Link
SG (1) SG10201808256PA (en)
WO (1) WO2020060481A1 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU2003274383A1 (en) * 2002-11-18 2004-06-15 Arm Limited Processor switching between secure and non-secure modes
CN103257929B (en) * 2013-04-18 2016-03-16 中国科学院计算技术研究所 A kind of virutal machine memory mapping method and system

Also Published As

Publication number Publication date
WO2020060481A1 (en) 2020-03-26

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