SG10201805213RA - SYSTEM AND METHOD FOR MAXIMIZING BANDWIDTH OF PCI EXPRESS (PCIe) PEER-TO-PEER (P2P) CONNECTION - Google Patents
SYSTEM AND METHOD FOR MAXIMIZING BANDWIDTH OF PCI EXPRESS (PCIe) PEER-TO-PEER (P2P) CONNECTIONInfo
- Publication number
- SG10201805213RA SG10201805213RA SG10201805213RA SG10201805213RA SG10201805213RA SG 10201805213R A SG10201805213R A SG 10201805213RA SG 10201805213R A SG10201805213R A SG 10201805213RA SG 10201805213R A SG10201805213R A SG 10201805213RA SG 10201805213R A SG10201805213R A SG 10201805213RA
- Authority
- SG
- Singapore
- Prior art keywords
- peer
- payload size
- maximum
- bandwidth
- pcie
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4265—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus
- G06F13/4278—Bus transfer protocol, e.g. handshake; Synchronisation on a point to point bus using an embedded synchronisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0688—Non-volatile semiconductor memory arrays
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Computer And Data Communications (AREA)
Abstract
OF THE DISCLOSURE A method and system for maximizing bandwidth of a Peripheral Component Interconnect Express (PCIe) Peer-to-Peer (P2P) connection determine a maximum bandwidth and a maximum read request size of a first device, determining a maximum bandwidth and a minimum payload size of a second device, calculate a calculated maximum payload size of the second device by using the maximum read request size of the first device and a bandwidth ratio between the first device and the second device, compare the minimum payload size of the second device with the calculated maximum payload size, and set an operational payload size of the second device to the calculated maximum payload size when the calculated maximum payload size is equal to or greater than the minimum payload size. FIG. 8A
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020170115404A KR102429904B1 (en) | 2017-09-08 | 2017-09-08 | Method and system for maximizing PCI-express bandwidth of peer-to-peer(P2P) connections |
Publications (1)
Publication Number | Publication Date |
---|---|
SG10201805213RA true SG10201805213RA (en) | 2019-04-29 |
Family
ID=65631392
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG10201805213RA SG10201805213RA (en) | 2017-09-08 | 2018-06-19 | SYSTEM AND METHOD FOR MAXIMIZING BANDWIDTH OF PCI EXPRESS (PCIe) PEER-TO-PEER (P2P) CONNECTION |
Country Status (4)
Country | Link |
---|---|
US (1) | US10642777B2 (en) |
KR (1) | KR102429904B1 (en) |
CN (1) | CN109471833B (en) |
SG (1) | SG10201805213RA (en) |
Families Citing this family (16)
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KR102429904B1 (en) * | 2017-09-08 | 2022-08-05 | 삼성전자주식회사 | Method and system for maximizing PCI-express bandwidth of peer-to-peer(P2P) connections |
US20190102287A1 (en) * | 2017-09-29 | 2019-04-04 | Intel Corporation | Remote persistent memory access device |
TWI636366B (en) * | 2017-11-22 | 2018-09-21 | 緯穎科技服務股份有限公司 | Processing method and computer system of data redundancy |
KR20200008483A (en) * | 2018-07-16 | 2020-01-28 | 삼성전자주식회사 | METHOD OF ACCESSING A DUAL LINE SSD DEVICE THROUGH PCIe EP AND NETWORK INTERFACE SIMULTANEOUSLY |
US11403253B2 (en) * | 2018-09-13 | 2022-08-02 | Microsoft Technology Licensing, Llc | Transport protocol and interface for efficient data transfer over RDMA fabric |
US11768613B2 (en) * | 2019-06-25 | 2023-09-26 | Micron Technology, Inc. | Aggregation and virtualization of solid state drives |
US10942881B2 (en) | 2019-06-25 | 2021-03-09 | Micron Technology, Inc. | Parallel operations in aggregated and virtualized solid state drives |
US11762798B2 (en) * | 2019-06-25 | 2023-09-19 | Micron Technology, Inc. | Aggregated and virtualized solid state drives with multiple host interfaces |
US11055249B2 (en) | 2019-06-25 | 2021-07-06 | Micron Technology, Inc. | Access optimization in aggregated and virtualized solid state drives |
US10942846B2 (en) | 2019-06-25 | 2021-03-09 | Micron Technology, Inc. | Aggregated and virtualized solid state drives accessed via multiple logical address spaces |
US11513923B2 (en) | 2019-06-25 | 2022-11-29 | Micron Technology, Inc. | Dynamic fail-safe redundancy in aggregated and virtualized solid state drives |
US11573708B2 (en) | 2019-06-25 | 2023-02-07 | Micron Technology, Inc. | Fail-safe redundancy in aggregated and virtualized solid state drives |
CN112579311B (en) * | 2019-09-30 | 2023-11-10 | 华为技术有限公司 | Method for accessing solid state disk and storage device |
US11372586B2 (en) * | 2020-05-19 | 2022-06-28 | Hewlett Packard Enterprise Development Lp | System and method for regulating NVMe-oF command requests and data flow across a network with mismatched rates |
CN112799982A (en) * | 2021-03-02 | 2021-05-14 | 井芯微电子技术(天津)有限公司 | Lumped RDMA link management method |
US11899935B2 (en) * | 2021-04-16 | 2024-02-13 | EMC IP Holding Company, LLC | System and method for user space NVMe-over-RDMA host library |
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US9684461B1 (en) * | 2016-10-31 | 2017-06-20 | International Business Machines Corporation | Dynamically adjusting read data return sizes based on memory interface bus utilization |
KR102429904B1 (en) * | 2017-09-08 | 2022-08-05 | 삼성전자주식회사 | Method and system for maximizing PCI-express bandwidth of peer-to-peer(P2P) connections |
-
2017
- 2017-09-08 KR KR1020170115404A patent/KR102429904B1/en active IP Right Grant
-
2018
- 2018-04-11 US US15/950,908 patent/US10642777B2/en active Active
- 2018-06-19 SG SG10201805213RA patent/SG10201805213RA/en unknown
- 2018-07-12 CN CN201810764962.2A patent/CN109471833B/en active Active
Also Published As
Publication number | Publication date |
---|---|
CN109471833A (en) | 2019-03-15 |
US20190079895A1 (en) | 2019-03-14 |
KR102429904B1 (en) | 2022-08-05 |
US10642777B2 (en) | 2020-05-05 |
KR20190028217A (en) | 2019-03-18 |
CN109471833B (en) | 2023-10-31 |
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