SG10201609844SA - Method and apparatus to control number of cores to transition operational states - Google Patents

Method and apparatus to control number of cores to transition operational states

Info

Publication number
SG10201609844SA
SG10201609844SA SG10201609844SA SG10201609844SA SG10201609844SA SG 10201609844S A SG10201609844S A SG 10201609844SA SG 10201609844S A SG10201609844S A SG 10201609844SA SG 10201609844S A SG10201609844S A SG 10201609844SA SG 10201609844S A SG10201609844S A SG 10201609844SA
Authority
SG
Singapore
Prior art keywords
cores
control number
operational states
transition operational
transition
Prior art date
Application number
SG10201609844SA
Inventor
Venkatesh Ramamurthy
Ripan Das
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of SG10201609844SA publication Critical patent/SG10201609844SA/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Power Sources (AREA)
SG10201609844SA 2015-12-24 2016-11-23 Method and apparatus to control number of cores to transition operational states SG10201609844SA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/757,561 US20170185128A1 (en) 2015-12-24 2015-12-24 Method and apparatus to control number of cores to transition operational states

Publications (1)

Publication Number Publication Date
SG10201609844SA true SG10201609844SA (en) 2017-07-28

Family

ID=59087067

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201609844SA SG10201609844SA (en) 2015-12-24 2016-11-23 Method and apparatus to control number of cores to transition operational states

Country Status (5)

Country Link
US (1) US20170185128A1 (en)
EP (1) EP3394704A4 (en)
CN (1) CN108292159A (en)
SG (1) SG10201609844SA (en)
WO (1) WO2017112311A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114527829B (en) * 2020-11-23 2024-01-30 Oppo广东移动通信有限公司 Clock gating circuit, chip and electronic equipment

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050050310A1 (en) * 2003-07-15 2005-03-03 Bailey Daniel W. Method, system, and apparatus for improving multi-core processor performance
US7451333B2 (en) * 2004-09-03 2008-11-11 Intel Corporation Coordinating idle state transitions in multi-core processors
KR101108397B1 (en) * 2005-06-10 2012-01-30 엘지전자 주식회사 Apparatus and method for controlling power supply in a multi-core processor
CN101241390B (en) * 2007-02-07 2011-04-13 华硕电脑股份有限公司 Multi- core processor efficiency regulation method
JP5235870B2 (en) * 2007-04-09 2013-07-10 パナソニック株式会社 Multiprocessor control device, control method thereof, and integrated circuit
CN100517181C (en) * 2007-08-16 2009-07-22 中国科学院计算技术研究所 Processor and its frequency-reducing device and method
US8156362B2 (en) * 2008-03-11 2012-04-10 Globalfoundries Inc. Hardware monitoring and decision making for transitioning in and out of low-power state
US20110213998A1 (en) * 2008-06-11 2011-09-01 John George Mathieson System and Method for Power Optimization
US8291249B2 (en) * 2009-09-25 2012-10-16 Advanced Micro Devices, Inc. Method and apparatus for transitioning devices between power states based on activity request frequency
US9104411B2 (en) * 2009-12-16 2015-08-11 Qualcomm Incorporated System and method for controlling central processing unit power with guaranteed transient deadlines
US8635476B2 (en) * 2010-12-22 2014-01-21 Via Technologies, Inc. Decentralized power management distributed among multiple processor cores
US8966305B2 (en) * 2011-06-30 2015-02-24 Advanced Micro Devices, Inc. Managing processor-state transitions
US8943340B2 (en) * 2011-10-31 2015-01-27 Intel Corporation Controlling a turbo mode frequency of a processor
US8874893B2 (en) * 2012-03-26 2014-10-28 International Business Machines Corporation Effect translation and assessment among microarchitecture components
WO2013165357A1 (en) * 2012-04-30 2013-11-07 Intel Corporation Master slave qpi protocol for coordinated idle power management in glueless and clustered systems
US20140095896A1 (en) * 2012-09-28 2014-04-03 Nicholas P. Carter Exposing control of power and clock gating for software
US9360918B2 (en) * 2012-12-21 2016-06-07 Advanced Micro Devices, Inc. Power control for multi-core data processor
US9377841B2 (en) * 2013-05-08 2016-06-28 Intel Corporation Adaptively limiting a maximum operating frequency in a multicore processor
US9304573B2 (en) * 2013-06-21 2016-04-05 Apple Inc. Dynamic voltage and frequency management based on active processors
US9495001B2 (en) * 2013-08-21 2016-11-15 Intel Corporation Forcing core low power states in a processor
US9507404B2 (en) * 2013-08-28 2016-11-29 Via Technologies, Inc. Single core wakeup multi-core synchronization mechanism
US9465432B2 (en) * 2013-08-28 2016-10-11 Via Technologies, Inc. Multi-core synchronization mechanism
US10088891B2 (en) * 2013-09-23 2018-10-02 Cornell University Multi-core computer processor based on a dynamic core-level power management for enhanced overall power efficiency
US9494998B2 (en) * 2013-12-17 2016-11-15 Intel Corporation Rescheduling workloads to enforce and maintain a duty cycle
US20150323975A1 (en) * 2014-05-12 2015-11-12 Qualcomm Innovation Center, Inc. SYNCHRONIZATION OF ACTIVITY OF MULTIPLE SUBSYSTEMS IN A SoC TO SAVE STATIC POWER
US9760158B2 (en) * 2014-06-06 2017-09-12 Intel Corporation Forcing a processor into a low power state
GB2532210A (en) * 2014-11-11 2016-05-18 Ibm System and method for controlling idle state exits to manage DI/DT issues
JP6418056B2 (en) * 2015-05-01 2018-11-07 富士通株式会社 Arithmetic processing device and control method of arithmetic processing device

Also Published As

Publication number Publication date
EP3394704A4 (en) 2019-08-07
EP3394704A1 (en) 2018-10-31
US20170185128A1 (en) 2017-06-29
CN108292159A (en) 2018-07-17
WO2017112311A1 (en) 2017-06-29

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