SG10201408366WA - Ip protection - Google Patents

Ip protection

Info

Publication number
SG10201408366WA
SG10201408366WA SG10201408366WA SG10201408366WA SG10201408366WA SG 10201408366W A SG10201408366W A SG 10201408366WA SG 10201408366W A SG10201408366W A SG 10201408366WA SG 10201408366W A SG10201408366W A SG 10201408366WA SG 10201408366W A SG10201408366W A SG 10201408366WA
Authority
SG
Singapore
Prior art keywords
protection
Prior art date
Application number
SG10201408366WA
Inventor
Soon Yoeng Tan
Teck Jung Tang
D Melville Ian
Yelei Vianna Yao
Yasushi Yamagata
Original Assignee
Globalfoundries Sg Pte Ltd
Ibm
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Globalfoundries Sg Pte Ltd, Ibm, Renesas Electronics Corp filed Critical Globalfoundries Sg Pte Ltd
Publication of SG10201408366WA publication Critical patent/SG10201408366WA/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/08—Intellectual property [IP] blocks or IP cores

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • User Interface Of Digital Computer (AREA)
SG10201408366WA 2011-06-16 2011-12-15 Ip protection SG10201408366WA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/161,514 US9069923B2 (en) 2011-06-16 2011-06-16 IP protection

Publications (1)

Publication Number Publication Date
SG10201408366WA true SG10201408366WA (en) 2015-04-29

Family

ID=47353029

Family Applications (2)

Application Number Title Priority Date Filing Date
SG10201408366WA SG10201408366WA (en) 2011-06-16 2011-12-15 Ip protection
SG2011093101A SG186529A1 (en) 2011-06-16 2011-12-15 Ip protection

Family Applications After (1)

Application Number Title Priority Date Filing Date
SG2011093101A SG186529A1 (en) 2011-06-16 2011-12-15 Ip protection

Country Status (2)

Country Link
US (2) US9069923B2 (en)
SG (2) SG10201408366WA (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7570796B2 (en) 2005-11-18 2009-08-04 Kla-Tencor Technologies Corp. Methods and systems for utilizing design data in combination with inspection data
KR101729669B1 (en) 2008-07-28 2017-04-24 케이엘에이-텐코어 코오포레이션 Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer
US8775101B2 (en) 2009-02-13 2014-07-08 Kla-Tencor Corp. Detecting defects on a wafer
US8781781B2 (en) 2010-07-30 2014-07-15 Kla-Tencor Corp. Dynamic care areas
US9170211B2 (en) 2011-03-25 2015-10-27 Kla-Tencor Corp. Design-based inspection using repeating structures
US9087367B2 (en) 2011-09-13 2015-07-21 Kla-Tencor Corp. Determining design coordinates for wafer defects
US8831334B2 (en) 2012-01-20 2014-09-09 Kla-Tencor Corp. Segmentation for wafer inspection
US8826200B2 (en) 2012-05-25 2014-09-02 Kla-Tencor Corp. Alteration for wafer inspection
US8826195B2 (en) 2012-06-05 2014-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Layout modification method and system
US9189844B2 (en) 2012-10-15 2015-11-17 Kla-Tencor Corp. Detecting defects on a wafer using defect-specific information
US9053527B2 (en) 2013-01-02 2015-06-09 Kla-Tencor Corp. Detecting defects on a wafer
US9134254B2 (en) * 2013-01-07 2015-09-15 Kla-Tencor Corp. Determining a position of inspection system output in design data space
US9311698B2 (en) 2013-01-09 2016-04-12 Kla-Tencor Corp. Detecting defects on a wafer using template image matching
KR102019534B1 (en) 2013-02-01 2019-09-09 케이엘에이 코포레이션 Detecting defects on a wafer using defect-specific and multi-channel information
US9865512B2 (en) 2013-04-08 2018-01-09 Kla-Tencor Corp. Dynamic design attributes for wafer inspection
US9310320B2 (en) 2013-04-15 2016-04-12 Kla-Tencor Corp. Based sampling and binning for yield critical defects
US9401016B2 (en) 2014-05-12 2016-07-26 Kla-Tencor Corp. Using high resolution full die image data for inspection
US9716035B2 (en) * 2014-06-20 2017-07-25 Taiwan Semiconductor Manufacturing Company, Ltd. Combination interconnect structure and methods of forming same
US20210349392A1 (en) * 2018-12-14 2021-11-11 North Sea Investment Company Ltd. Method for creation of different designs by combining a set of pre-defined disjoint masks

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070174638A1 (en) 2006-01-20 2007-07-26 National Taiwan University Method used for digital right management of system-on-chip IP by making use of system platform
US7904855B2 (en) * 2006-04-14 2011-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for partially removing circuit patterns from a multi-project wafer
US7851272B2 (en) * 2007-05-30 2010-12-14 Taiwan Semiconductor Manufacturing Co., Ltd. Multi-project wafer and method of making same
US20090321870A1 (en) * 2008-06-27 2009-12-31 United Microelectronics Corp. Shuttle wafer and method of fabricating the same
US20100068832A1 (en) * 2008-09-15 2010-03-18 Hui-Shen Shih Method for the protection of information in multi-project wafers
US9140978B2 (en) * 2010-10-12 2015-09-22 Weng-Dah Ken Semiconductor multi-project or multi-product wafer process

Also Published As

Publication number Publication date
US20120319246A1 (en) 2012-12-20
SG186529A1 (en) 2013-01-30
US9947645B2 (en) 2018-04-17
US9069923B2 (en) 2015-06-30
US20150294964A1 (en) 2015-10-15

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