SG10201408366WA - Ip protection - Google Patents
Ip protectionInfo
- Publication number
- SG10201408366WA SG10201408366WA SG10201408366WA SG10201408366WA SG10201408366WA SG 10201408366W A SG10201408366W A SG 10201408366WA SG 10201408366W A SG10201408366W A SG 10201408366WA SG 10201408366W A SG10201408366W A SG 10201408366WA SG 10201408366W A SG10201408366W A SG 10201408366WA
- Authority
- SG
- Singapore
- Prior art keywords
- protection
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/08—Intellectual property [IP] blocks or IP cores
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- User Interface Of Digital Computer (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/161,514 US9069923B2 (en) | 2011-06-16 | 2011-06-16 | IP protection |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SG10201408366WA true SG10201408366WA (en) | 2015-04-29 |
Family
ID=47353029
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG10201408366WA SG10201408366WA (en) | 2011-06-16 | 2011-12-15 | Ip protection |
| SG2011093101A SG186529A1 (en) | 2011-06-16 | 2011-12-15 | Ip protection |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SG2011093101A SG186529A1 (en) | 2011-06-16 | 2011-12-15 | Ip protection |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US9069923B2 (en) |
| SG (2) | SG10201408366WA (en) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7570796B2 (en) | 2005-11-18 | 2009-08-04 | Kla-Tencor Technologies Corp. | Methods and systems for utilizing design data in combination with inspection data |
| KR101623747B1 (en) | 2008-07-28 | 2016-05-26 | 케이엘에이-텐코어 코오포레이션 | Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer |
| US8775101B2 (en) | 2009-02-13 | 2014-07-08 | Kla-Tencor Corp. | Detecting defects on a wafer |
| US8781781B2 (en) | 2010-07-30 | 2014-07-15 | Kla-Tencor Corp. | Dynamic care areas |
| US9170211B2 (en) | 2011-03-25 | 2015-10-27 | Kla-Tencor Corp. | Design-based inspection using repeating structures |
| US9087367B2 (en) | 2011-09-13 | 2015-07-21 | Kla-Tencor Corp. | Determining design coordinates for wafer defects |
| US8831334B2 (en) | 2012-01-20 | 2014-09-09 | Kla-Tencor Corp. | Segmentation for wafer inspection |
| US8826200B2 (en) | 2012-05-25 | 2014-09-02 | Kla-Tencor Corp. | Alteration for wafer inspection |
| US8826195B2 (en) * | 2012-06-05 | 2014-09-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Layout modification method and system |
| US9189844B2 (en) | 2012-10-15 | 2015-11-17 | Kla-Tencor Corp. | Detecting defects on a wafer using defect-specific information |
| US9053527B2 (en) | 2013-01-02 | 2015-06-09 | Kla-Tencor Corp. | Detecting defects on a wafer |
| US9134254B2 (en) * | 2013-01-07 | 2015-09-15 | Kla-Tencor Corp. | Determining a position of inspection system output in design data space |
| US9311698B2 (en) | 2013-01-09 | 2016-04-12 | Kla-Tencor Corp. | Detecting defects on a wafer using template image matching |
| WO2014149197A1 (en) | 2013-02-01 | 2014-09-25 | Kla-Tencor Corporation | Detecting defects on a wafer using defect-specific and multi-channel information |
| US9865512B2 (en) | 2013-04-08 | 2018-01-09 | Kla-Tencor Corp. | Dynamic design attributes for wafer inspection |
| US9310320B2 (en) | 2013-04-15 | 2016-04-12 | Kla-Tencor Corp. | Based sampling and binning for yield critical defects |
| US9401016B2 (en) * | 2014-05-12 | 2016-07-26 | Kla-Tencor Corp. | Using high resolution full die image data for inspection |
| US9716035B2 (en) * | 2014-06-20 | 2017-07-25 | Taiwan Semiconductor Manufacturing Company, Ltd. | Combination interconnect structure and methods of forming same |
| CN115268222B (en) * | 2018-12-14 | 2024-04-30 | 深圳市奇普乐芯片技术有限公司 | Method, IC die and semiconductor device |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070174638A1 (en) | 2006-01-20 | 2007-07-26 | National Taiwan University | Method used for digital right management of system-on-chip IP by making use of system platform |
| US7904855B2 (en) * | 2006-04-14 | 2011-03-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for partially removing circuit patterns from a multi-project wafer |
| US7851272B2 (en) * | 2007-05-30 | 2010-12-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-project wafer and method of making same |
| US20090321870A1 (en) * | 2008-06-27 | 2009-12-31 | United Microelectronics Corp. | Shuttle wafer and method of fabricating the same |
| US20100068832A1 (en) * | 2008-09-15 | 2010-03-18 | Hui-Shen Shih | Method for the protection of information in multi-project wafers |
| US9140978B2 (en) * | 2010-10-12 | 2015-09-22 | Weng-Dah Ken | Semiconductor multi-project or multi-product wafer process |
-
2011
- 2011-06-16 US US13/161,514 patent/US9069923B2/en active Active
- 2011-12-15 SG SG10201408366WA patent/SG10201408366WA/en unknown
- 2011-12-15 SG SG2011093101A patent/SG186529A1/en unknown
-
2015
- 2015-06-26 US US14/751,170 patent/US9947645B2/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| US20150294964A1 (en) | 2015-10-15 |
| US9947645B2 (en) | 2018-04-17 |
| SG186529A1 (en) | 2013-01-30 |
| US9069923B2 (en) | 2015-06-30 |
| US20120319246A1 (en) | 2012-12-20 |
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