SG10201406847VA - Trace structure of fine-pitch pattern - Google Patents

Trace structure of fine-pitch pattern

Info

Publication number
SG10201406847VA
SG10201406847VA SG10201406847VA SG10201406847VA SG10201406847VA SG 10201406847V A SG10201406847V A SG 10201406847VA SG 10201406847V A SG10201406847V A SG 10201406847VA SG 10201406847V A SG10201406847V A SG 10201406847VA SG 10201406847V A SG10201406847V A SG 10201406847VA
Authority
SG
Singapore
Prior art keywords
fine
pitch pattern
trace structure
trace
pitch
Prior art date
Application number
SG10201406847VA
Inventor
Hsieh Yung-Wei
Shih Cheng-Hung
Wang Kai-Yi
Huang Heh-Chang
Chen Po-Hao
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Publication of SG10201406847VA publication Critical patent/SG10201406847VA/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • ing And Chemical Polishing (AREA)
  • Wire Bonding (AREA)
SG10201406847VA 2014-07-15 2014-10-23 Trace structure of fine-pitch pattern SG10201406847VA (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103124328A TW201603227A (en) 2014-07-15 2014-07-15 Routing structure for fine-pitch pattern

Publications (1)

Publication Number Publication Date
SG10201406847VA true SG10201406847VA (en) 2016-02-26

Family

ID=52208812

Family Applications (1)

Application Number Title Priority Date Filing Date
SG10201406847VA SG10201406847VA (en) 2014-07-15 2014-10-23 Trace structure of fine-pitch pattern

Country Status (6)

Country Link
US (1) US20160020166A1 (en)
JP (1) JP2016021543A (en)
KR (1) KR20160008941A (en)
CN (2) CN105304621A (en)
SG (1) SG10201406847VA (en)
TW (1) TW201603227A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201603227A (en) * 2014-07-15 2016-01-16 頎邦科技股份有限公司 Routing structure for fine-pitch pattern
JP6725388B2 (en) * 2016-09-28 2020-07-15 京セラ株式会社 Printed wiring board
TWI711347B (en) 2019-12-31 2020-11-21 頎邦科技股份有限公司 Flip chip interconnection and circuit substrate thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3198484B2 (en) * 1991-10-14 2001-08-13 ソニー株式会社 Printed circuit board manufacturing method
JP2000208881A (en) * 1999-01-12 2000-07-28 Nitto Denko Corp Printed wiring board and conductor pattern formation method for it
JP4137412B2 (en) * 2001-07-30 2008-08-20 株式会社住友金属エレクトロデバイス Manufacturing method of wiring board for electronic parts
US7518218B2 (en) * 2005-03-03 2009-04-14 Aeroflex Colorado Springs, Inc. Total ionizing dose suppression transistor architecture
CN101026931B (en) * 2006-02-24 2011-10-19 佛山市顺德区顺达电脑厂有限公司 Right-angled signal line making method and its circuit board
TWI434115B (en) * 2011-04-26 2014-04-11 Au Optronics Corp Fan-out circuit
CN103050379B (en) * 2012-12-10 2015-03-04 华映视讯(吴江)有限公司 Method for forming narrow-pitch lines
TW201603227A (en) * 2014-07-15 2016-01-16 頎邦科技股份有限公司 Routing structure for fine-pitch pattern

Also Published As

Publication number Publication date
US20160020166A1 (en) 2016-01-21
JP2016021543A (en) 2016-02-04
CN105304621A (en) 2016-02-03
CN204067357U (en) 2014-12-31
KR20160008941A (en) 2016-01-25
TW201603227A (en) 2016-01-16

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