SE9803632D0 - A processor - Google Patents
A processorInfo
- Publication number
- SE9803632D0 SE9803632D0 SE9803632A SE9803632A SE9803632D0 SE 9803632 D0 SE9803632 D0 SE 9803632D0 SE 9803632 A SE9803632 A SE 9803632A SE 9803632 A SE9803632 A SE 9803632A SE 9803632 D0 SE9803632 D0 SE 9803632D0
- Authority
- SE
- Sweden
- Prior art keywords
- register file
- job
- processor
- file memory
- priority
- Prior art date
Links
- 230000015654 memory Effects 0.000 abstract 6
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multimedia (AREA)
- Exchange Systems With Centralized Control (AREA)
Abstract
In a processor separate register file memories (33, 35) are arranged in a pipelined manner. The processor executes jobs having different priorities using for each job a register file stored in a register file memory assigned to the priority of the job. During the execution of the job data corresponding to a successive job of the same priority, the data of which for example is arranged ina queue (9), are stored in a standby register file memory (35). When finishing the ongoing job, the successive job having the same priority can start to be executed much faster since no or very little time is required for changing the contents of the register file memory. Instead, all that needs to be performed is to switch (37) to the standby register file memory to make it be connected to the Arithmetic Logic Unit ALU (27) of the processor. The previously active register file memory (33) will then be the standby one, and can receive a new register file for the same priority or a different priority when said successive job is executed. The processor is particularly useful for application in which jobs are frequently changed, such as a processor connected to a telephone exchange.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9803632A SE9803632D0 (en) | 1998-10-22 | 1998-10-22 | A processor |
AU14292/00A AU1429200A (en) | 1998-10-22 | 1999-10-22 | A processor |
PCT/SE1999/001904 WO2000023891A1 (en) | 1998-10-22 | 1999-10-22 | A processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE9803632A SE9803632D0 (en) | 1998-10-22 | 1998-10-22 | A processor |
Publications (1)
Publication Number | Publication Date |
---|---|
SE9803632D0 true SE9803632D0 (en) | 1998-10-22 |
Family
ID=20413063
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE9803632A SE9803632D0 (en) | 1998-10-22 | 1998-10-22 | A processor |
Country Status (3)
Country | Link |
---|---|
AU (1) | AU1429200A (en) |
SE (1) | SE9803632D0 (en) |
WO (1) | WO2000023891A1 (en) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6389449B1 (en) | 1998-12-16 | 2002-05-14 | Clearwater Networks, Inc. | Interstream control and communications for multi-streaming digital processors |
US7257814B1 (en) | 1998-12-16 | 2007-08-14 | Mips Technologies, Inc. | Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors |
US7529907B2 (en) | 1998-12-16 | 2009-05-05 | Mips Technologies, Inc. | Method and apparatus for improved computer load and store operations |
US7020879B1 (en) | 1998-12-16 | 2006-03-28 | Mips Technologies, Inc. | Interrupt and exception handling for multi-streaming digital processors |
US7237093B1 (en) | 1998-12-16 | 2007-06-26 | Mips Technologies, Inc. | Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams |
US6292888B1 (en) * | 1999-01-27 | 2001-09-18 | Clearwater Networks, Inc. | Register transfer unit for electronic processor |
US7035997B1 (en) | 1998-12-16 | 2006-04-25 | Mips Technologies, Inc. | Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors |
DE60130836T2 (en) * | 2000-06-12 | 2008-07-17 | Broadcom Corp., Irvine | Architecture and method for context switching |
JP2004518183A (en) | 2000-07-14 | 2004-06-17 | クリアウオーター・ネツトワークス・インコーポレイテツド | Instruction fetch and dispatch in multithreaded systems |
US10136165B2 (en) * | 2011-09-14 | 2018-11-20 | Mobitv, Inc. | Distributed scalable encoder resources for live streams |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69034028T2 (en) * | 1989-05-04 | 2003-10-09 | Texas Instruments Inc., Dallas | Method and system for determining min / max values |
US5357617A (en) * | 1991-11-22 | 1994-10-18 | International Business Machines Corporation | Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor |
US5655132A (en) * | 1994-08-08 | 1997-08-05 | Rockwell International Corporation | Register file with multi-tasking support |
US5727211A (en) * | 1995-11-09 | 1998-03-10 | Chromatic Research, Inc. | System and method for fast context switching between tasks |
JP3605978B2 (en) * | 1997-01-17 | 2004-12-22 | 松下電器産業株式会社 | Microcomputer |
US5949994A (en) * | 1997-02-12 | 1999-09-07 | The Dow Chemical Company | Dedicated context-cycling computer with timed context |
-
1998
- 1998-10-22 SE SE9803632A patent/SE9803632D0/en unknown
-
1999
- 1999-10-22 AU AU14292/00A patent/AU1429200A/en not_active Abandoned
- 1999-10-22 WO PCT/SE1999/001904 patent/WO2000023891A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
AU1429200A (en) | 2000-05-08 |
WO2000023891A1 (en) | 2000-04-27 |
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