SE9803632D0 - A processor - Google Patents

A processor

Info

Publication number
SE9803632D0
SE9803632D0 SE9803632A SE9803632A SE9803632D0 SE 9803632 D0 SE9803632 D0 SE 9803632D0 SE 9803632 A SE9803632 A SE 9803632A SE 9803632 A SE9803632 A SE 9803632A SE 9803632 D0 SE9803632 D0 SE 9803632D0
Authority
SE
Sweden
Prior art keywords
register file
job
processor
file memory
priority
Prior art date
Application number
SE9803632A
Other languages
Swedish (sv)
Inventor
Lars-Erik Lundstroem
Kari Hintukainen
Olav Tveite
Karl Nils Isaksson
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9803632A priority Critical patent/SE9803632D0/en
Publication of SE9803632D0 publication Critical patent/SE9803632D0/en
Priority to AU14292/00A priority patent/AU1429200A/en
Priority to PCT/SE1999/001904 priority patent/WO2000023891A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098Register arrangements
    • G06F9/3012Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

In a processor separate register file memories (33, 35) are arranged in a pipelined manner. The processor executes jobs having different priorities using for each job a register file stored in a register file memory assigned to the priority of the job. During the execution of the job data corresponding to a successive job of the same priority, the data of which for example is arranged ina queue (9), are stored in a standby register file memory (35). When finishing the ongoing job, the successive job having the same priority can start to be executed much faster since no or very little time is required for changing the contents of the register file memory. Instead, all that needs to be performed is to switch (37) to the standby register file memory to make it be connected to the Arithmetic Logic Unit ALU (27) of the processor. The previously active register file memory (33) will then be the standby one, and can receive a new register file for the same priority or a different priority when said successive job is executed. The processor is particularly useful for application in which jobs are frequently changed, such as a processor connected to a telephone exchange.
SE9803632A 1998-10-22 1998-10-22 A processor SE9803632D0 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
SE9803632A SE9803632D0 (en) 1998-10-22 1998-10-22 A processor
AU14292/00A AU1429200A (en) 1998-10-22 1999-10-22 A processor
PCT/SE1999/001904 WO2000023891A1 (en) 1998-10-22 1999-10-22 A processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9803632A SE9803632D0 (en) 1998-10-22 1998-10-22 A processor

Publications (1)

Publication Number Publication Date
SE9803632D0 true SE9803632D0 (en) 1998-10-22

Family

ID=20413063

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9803632A SE9803632D0 (en) 1998-10-22 1998-10-22 A processor

Country Status (3)

Country Link
AU (1) AU1429200A (en)
SE (1) SE9803632D0 (en)
WO (1) WO2000023891A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6389449B1 (en) 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors
US7257814B1 (en) 1998-12-16 2007-08-14 Mips Technologies, Inc. Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors
US7529907B2 (en) 1998-12-16 2009-05-05 Mips Technologies, Inc. Method and apparatus for improved computer load and store operations
US7020879B1 (en) 1998-12-16 2006-03-28 Mips Technologies, Inc. Interrupt and exception handling for multi-streaming digital processors
US7237093B1 (en) 1998-12-16 2007-06-26 Mips Technologies, Inc. Instruction fetching system in a multithreaded processor utilizing cache miss predictions to fetch instructions from multiple hardware streams
US6292888B1 (en) * 1999-01-27 2001-09-18 Clearwater Networks, Inc. Register transfer unit for electronic processor
US7035997B1 (en) 1998-12-16 2006-04-25 Mips Technologies, Inc. Methods and apparatus for improving fetching and dispatch of instructions in multithreaded processors
DE60130836T2 (en) * 2000-06-12 2008-07-17 Broadcom Corp., Irvine Architecture and method for context switching
JP2004518183A (en) 2000-07-14 2004-06-17 クリアウオーター・ネツトワークス・インコーポレイテツド Instruction fetch and dispatch in multithreaded systems
US10136165B2 (en) * 2011-09-14 2018-11-20 Mobitv, Inc. Distributed scalable encoder resources for live streams

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69034028T2 (en) * 1989-05-04 2003-10-09 Texas Instruments Inc., Dallas Method and system for determining min / max values
US5357617A (en) * 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
US5655132A (en) * 1994-08-08 1997-08-05 Rockwell International Corporation Register file with multi-tasking support
US5727211A (en) * 1995-11-09 1998-03-10 Chromatic Research, Inc. System and method for fast context switching between tasks
JP3605978B2 (en) * 1997-01-17 2004-12-22 松下電器産業株式会社 Microcomputer
US5949994A (en) * 1997-02-12 1999-09-07 The Dow Chemical Company Dedicated context-cycling computer with timed context

Also Published As

Publication number Publication date
AU1429200A (en) 2000-05-08
WO2000023891A1 (en) 2000-04-27

Similar Documents

Publication Publication Date Title
JP3776449B2 (en) Multitasking low power controller
KR970016945A (en) Multi-instruction execution method and superscalar microprocessor
NZ236142A (en) Data processor skips execution of instructions in queue that are tagged as requiring unavailable data
KR940015852A (en) Handler with long instruction word
MY122682A (en) System and method for performing context switching and rescheduling of a processor
JPH04172533A (en) Electronic computer
SE9803632D0 (en) A processor
JP3595562B2 (en) Data processor
JP2005050208A (en) Memory managing system in multi-task system and task controller
EP1065586A2 (en) Computer system comprising a plurality of parallel processors
Lindh et al. From single to multiprocessor real-time kernels in hardware
KR940002322B1 (en) Method of transferring register allocation
US20050125801A1 (en) Method and apparartus for context switching in computer operating systems
JPWO2008114415A1 (en) Multi-processing system
JP2003058381A (en) Processor realizing exception processing setting by program
DE3687159D1 (en) MULTIPROCESSOR DATA PROCESSING SYSTEM.
JP2008015638A (en) Data processor
JP2008225710A (en) Computer system and process-switching method used in the system
JPH11184828A (en) Test system for multiprocessor system
JPH1091593A (en) Data processor provided with microprocessor and optional calculation unit
JPS5617441A (en) Program interruption system
JPH05165652A (en) Task switching control method
JP2001147822A (en) Real time monitor
RU1777147C (en) Multiprogramming computer
JPS62151942A (en) Task changing-over system