SE8804700A - - Google Patents

Info

Publication number
SE8804700A
SE8804700A SE8804700A SE8804700A SE8804700A SE 8804700 A SE8804700 A SE 8804700A SE 8804700 A SE8804700 A SE 8804700A SE 8804700 A SE8804700 A SE 8804700A SE 8804700 A SE8804700 A SE 8804700A
Authority
SE
Sweden
Prior art keywords
data
memory
control unit
computer system
buses
Prior art date
Application number
SE8804700A
Other languages
Unknown language ( )
Other versions
SE461813B (en
SE8804700D0 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of SE8804700A publication Critical patent/SE8804700A/
Publication of SE8804700D0 publication Critical patent/SE8804700D0/en
Priority to DE68928454T priority Critical patent/DE68928454T2/en
Priority to EP89907854A priority patent/EP0424432B1/en
Priority to AT89907854T priority patent/ATE160454T1/en
Priority to PCT/SE1989/000369 priority patent/WO1990000283A1/en
Priority to JP1507284A priority patent/JPH03505793A/en
Publication of SE461813B publication Critical patent/SE461813B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0813—Multiuser, multiprocessor or multiprocessing cache systems with a network or matrix configuration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0817—Cache consistency protocols using directory methods
    • G06F12/0824—Distributed directories, e.g. linked lists of caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)

Abstract

The present invention relates to a computer system with scalable multiprocessor architecture with a distributed physical memory which supports data with a divided virtual memory. There is no connection at all between the location of a data element in the machine and its virtual address. In particular, there is no home position in which a data element normally has to be situated. Instead, data automatically moves wherever it is required, which reduces access times and data traffic. The computer system consists of a hierarchy of buses and data control units which interlink an arbitrary number of processor/memory pairs, which constitute the only data memory of the system. Each data control unit has a set- associative status memory which contains information for data elements under its control. The control unit controls data transactions by sensing buses above and below it. The data access protocol used ensures automatic transfer, duplication and rearrangement of data with retention of data coherence and without loss of data from the system. <IMAGE>
SE8804700A 1988-07-04 1988-12-30 Multiprocessor architecture comprising processor/memory pairs interconnected with one or more buses in a hierarchical system SE461813B (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE68928454T DE68928454T2 (en) 1988-07-04 1989-06-29 MULTIPROCESSOR SYSTEM WITH HIERARCHIC CACHE STORAGE ARRANGEMENT
EP89907854A EP0424432B1 (en) 1988-07-04 1989-06-29 Multiprocessor system including a hierarchical cache memory system
AT89907854T ATE160454T1 (en) 1988-07-04 1989-06-29 MULTIPROCESSOR SYSTEM WITH HIERARCHICAL CACHE MEMORY ARRANGEMENT
PCT/SE1989/000369 WO1990000283A1 (en) 1988-07-04 1989-06-29 Multiprocessor system including a hierarchical cache memory system
JP1507284A JPH03505793A (en) 1988-07-04 1989-06-29 Multiprocessor system including cache memory system with hierarchical structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE8802495A SE8802495D0 (en) 1988-07-04 1988-07-04 COMPUTER SYSTEM

Publications (3)

Publication Number Publication Date
SE8804700A true SE8804700A (en) 1988-12-30
SE8804700D0 SE8804700D0 (en) 1988-12-30
SE461813B SE461813B (en) 1990-03-26

Family

ID=20372807

Family Applications (2)

Application Number Title Priority Date Filing Date
SE8802495A SE8802495D0 (en) 1988-07-04 1988-07-04 COMPUTER SYSTEM
SE8804700A SE461813B (en) 1988-07-04 1988-12-30 Multiprocessor architecture comprising processor/memory pairs interconnected with one or more buses in a hierarchical system

Family Applications Before (1)

Application Number Title Priority Date Filing Date
SE8802495A SE8802495D0 (en) 1988-07-04 1988-07-04 COMPUTER SYSTEM

Country Status (1)

Country Link
SE (2) SE8802495D0 (en)

Also Published As

Publication number Publication date
SE8802495D0 (en) 1988-07-04
SE461813B (en) 1990-03-26
SE8804700D0 (en) 1988-12-30

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