SE7111047L - - Google Patents
Info
- Publication number
- SE7111047L SE7111047L SE7111047A SE7111047A SE7111047L SE 7111047 L SE7111047 L SE 7111047L SE 7111047 A SE7111047 A SE 7111047A SE 7111047 A SE7111047 A SE 7111047A SE 7111047 L SE7111047 L SE 7111047L
- Authority
- SE
- Sweden
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H01L27/1124—
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- H01L29/00—
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- H01L29/0638—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/27—ROM only
- H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
- H10B20/36—Gate programmed, e.g. different gate material or no gate
- H10B20/363—Gate conductor programmed
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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SE7111047T |
Publications (1)
Publication Number | Publication Date |
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SE7111047L true SE7111047L (en)) | 1972-03-03 |
Family
ID=43984301
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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SE7111047A SE7111047L (en)) |
Country Status (1)
Country | Link |
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SE (1) | SE7111047L (en)) |
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0
- SE SE7111047A patent/SE7111047L/xx unknown