SE516703C2 - Device, system and method related to routing of packets in a data communication network - Google Patents

Abstract

The present invention relates to an arrangement (20), system and a method respectively for forwarding data packets through a routing device including router storing means (23) including a digital search tree, a trie (25), the searching of which comprises traversion the tree from the root to a leaf through a number of nodes. In addition to the trie (25) a cache memory (24) is provided for storing of a number of indices to the leaves containing next-hop addresses. For looking-up a next-hop address for an incoming packet, a search is performed at least in the cache memory (24), and in absence of a cache hit, a search is also performed in the trie (25). This can be done in parallel or in series.

Description

20 25 30 516 var, so »nu 2 use a central processor soul serves all the input ports of a routing device to perform address lookup. A start packet is then received in the processor, also called a forwarding machine, which uses the destination address to determine which output port is relevant to the packet and its next-hop address.

In a routing device in which "next-hop" information is stored in a conventional table, there must be some kind of mapping between an incoming IP address and the memory address or index where its next-hop information is stored. In order to perform an IP address to a correct address lookup, memory address is transformed which is then followed by a lookup in the table.

To speed up the search, it is known to use so-called digital search trees as storage means in many known devices. Such search trees are also called "tries" (compare retrieval). In a tri-based routing device, there is no corresponding type of mapping, as referred to above, between the IP address and the location for storing the next-hop information. Instead, an analysis of the incoming IP address is performed in several steps. Each step returns a new node in the digital search tree in which leaves correspond to entries in a file. Search continues from the root to a leaf. The (each) node is then analyzed so that it can be determined which of its children is the next step towards the end node (compare leaves as referred to above) which contains the next jump information. This means that trees are passed through node by node and in each step the information must be retrieved. The consequence of this is that a look-up to find “next-hop” information involves a review of the digital search tree, which technically means that memory accesses must be done several times. For routing devices where the storage means consists exclusively of tables, the next-jump tables will be very large. In order to be able to perform a quick look-up, such tables are stored in fast and expensive memories. In order to further increase the performance of a routing device, the memories are provided with even faster, fully acoustic caches so that that a copy of a recently found next-hop information can be stored therein.A cache memory is a high-speed memory that stores data that the computer can access very quickly.It can be an independent high-speed storage device or it can be a certain section of a main memory.

This works because there is a temporary 'location' connection between the memory access, or in other words, if the next hope information for an address has been looked up, it is very likely that the same information will be needed again in the near future. The reason for this is that an IP packet is rarely sent alone but as part of a flow of several packets.

In routing devices in which the storage means are implemented as a digital search tree, or a trie, as referred to above, the search tree itself may be compressed in various ways and it may be made so small that the table is represented by a search tree. there will be room for it in the internal data cache of a commercial processor. The result is that a processor can quickly. However, all memory accesses to find the node with the next-jump information do next-jump lookups must be performed. However, each such memory access is demanding, and since a large number of memory accesses may be required for each new address, this significantly limits the performance of a routing device. Various tri-based routing devices are known, see for example “Small Forwarding Tables for Fast Routing Lookups”, 1997: 02, Department of Computer by Mikael Degermark et al, Research Report Luleå University of Technology, Science and Electrical Engineering, Fast Division of Computer Communication and IP Routing with LC-Tries ”, Karlsson, Dr Dobb's Journal, August 1998, pages 70-75. by Stefan Nilsson, Gunnar 10 15 20 25 30 516 703 4 In general, several ways of using compression technique algorithms applied to routing are known.

However, none of them provide a satisfactory solution that enables fast and efficient retrieval of next-jump information.

DISCLOSURE OF THE INVENTION What is needed, therefore, is a device for transmitting data packets through a high performance routing device.

In particular, a device is needed by which the look-up of the next efficient fast method, especially so that the number of next hop addresses that can be found per hop addresses can be performed on one and unit of time becomes high and especially higher than with hitherto known devices. A device is also needed through which a packet can be transported in a fast and secure way through a node in an IP-based network. In particular, a device is needed through which the number of memory accesses can be reduced, and thus increase performance. A tri-based routing device is also needed that meets the above mentioned goals. A device of the above-mentioned type which is cheap and easy to build is especially needed.

A method of forwarding the routing device is also needed by which the above-mentioned goal can be met or a data packet through one is fulfilled. In addition, a communication system, network of communication systems, is needed, which includes a number of routing devices, through which the above-mentioned goals can be met. A data packet is provided within a packet-switched network, or between networks, by a trie. The search in such a trie involves traversing the tree from the root to a leaf through a number of nodes. Control means, for example a forwarding machine, which are to be provided, include a search engine for controlling address lookup for incoming packets.

A cache is arranged in addition to the digital search tree. In the cache there are a number of indexes to the leaves in said trie for a number of next jump addresses. To look up a next-hop address for an incoming packet, a search is performed at least in the cache.

Control means are used to receive incoming addresses, for example IP addresses, and to initiate a look-up of the corresponding next-hop address, which includes a look-up in the cache and a review of the digital search tree (if necessary).

In particular, a transversal of a digital search tree is initiated substantially simultaneously with the lookup in the cache. Alternatively, the search tree if one is initiated only the traversal of the digital lookup in the cache does not succeed, ie if the address with to This either the search is done in the digital search tree parallel index the next-jump address is not found. means with it and the lookup in the cache or it is initialized if it becomes a cache hit. If the cache lookup does not perform any search in the trien in parallel, the traversal of the search tree as soon as there is a hit in the cache is essentially interrupted.

In particular, indexes to the leaves for a number of the most recently searched next-jump addresses are stored in the cache. The index cache is preferably formed in such a way that the least recently used addresses in the cache are successively replaced by more recently opened ones or an address is defined. In exemplary embodiments n u a nu no nøoøwu v 10 15 20 25 30 516 703 'In 6 time intervals for replacing addresses in the cache so that addresses which have not been used during such an interval are replaced by new addresses. This can be done in different ways, using different priority requirements and so on. shorter than for a cache access search tree. access time it In particular, a memory access in the digital cache can be a direct mapping cache, a "set" associative cache or a fully associative cache.

In a particularly advantageous embodiment, the device is implemented as an FPGA (Field Programmable Gate Array) chip. In an alternative implementation, the device is implemented as an ASIC (Application Specification Integrated Circuit) chip.

The storage means, ie the digital search tree, can be implemented as a digital tree structure. Alternatively, which is stored "on-chip". the “off-chip” is stored.

In particular, the cache memory is arranged "on-chip".

In a special implementation, the device comprises an IP router, ie an Internet router. In particular, the routing table consisting of a digital search tree comprises a compressed data structure. The Patricia trie digital search tree may include an LC trie, or any other suitable known trie.

In a particularly advantageous embodiment, a number of addresses are displayed in parallel. This can also be implemented by any kind of pipe-line procedure.

Therefore, a method of forwarding packets through a routing device in a packet-switched data network is also provided.

The routing device includes control means (a forwarding and / or island 10 15 20 25 30 516 703 u oas n. A search tree. The method includes the steps of storing indexes to the next machine) and router storage means comprising digitally the jump addresses of a number of data packet addresses in a cache; use the cache and a traversal of the digital search tree to find an index to the next-jump address or the leaf that contains the next-jump address; interrupt the traversal of the digital search tree if there is a hit in the cache, otherwise continue traversing the digital search tree until the next jump address is found. This is followed by the steps of retrieving the next-jump address information and forwarding the packet to the relevant exit port using the next-jump information found.

In particular, the method includes the steps of first performing a lookup 'in the cache, and if there is no cache hit, initiating a traversal of the digital search tree. In performing a cache memory simultaneously and in parallel and alternative implementation, the method includes the steps of initiating a traversal of the digital search tree and interrupting the traversal of the digital search tree if it has become a cache hit, and otherwise continuing with the traversing until the leaf containing the next-hop address is found in the search tree. The method includes in particular the step of, when a next-hop address is found by traversing the digital search tree, storing the index to said next-hop address in the cache, for example replacing the least recently accessed address information if there is no free space in the cache with the index to the most recently used address information.

According to various embodiments, the cache memory is, for example, a direct mapping cache, a "set" associative or a fully associative index cache arranged "on-chip" for an FPGA or an ASIC used for the implementation of the routing device. Furthermore, the method is characterized by the step of looking up a number of next-hop addresses substantially in parallel (or in accordance with a pipe-line method).

A packet data communication system is also indicated which comprises a number of routing devices within a network or for connecting networks, each routing device comprising a number of input and output ports, control means with a number of forwarding machines, router storage means including a digital search tree or a trio containing the next hop address information_ At least a number of the routing devices include a cache memory to store indexes to a number of next hop addresses contained in the digital search tree. To find a next jump address, a lookup is performed at least in the cache.

In particular, a traversal of the digital search tree is initiated substantially simultaneously with where. does not become a cache hit.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will be further described in the following, in a non-limiting manner, and with reference to the accompanying figures in which: Fig. 1 is a simplified, schematic illustration of a device according to the invention, Fig. 2 shows storage of nodes / a leaf in a memory, FIG. 3 is a simplified illustration of a trie, FIG. 4 illustrates in more detail an embodiment of a device according to the invention, FIG. 5 shows another embodiment of a device according to the invention, FIG. 6 is a flowchart schematically illustrating the look-up of a next-hop address according to the invention, Fig. 7 is a flowchart showing tri-memory access, and Fig. 8 is a flowchart illustrating how a next-hop address is found using a trie and a cache according to the invention.

DETAILED DESCRIPTION OF THE INVENTION Fig. 1 describes a device according to the invention in a simplified manner. According to the invention, the temporary location between the packets is considered even if a tri-based routing device is used.

It is assumed here that packets are received by control means 2. In this special exemplary embodiment, it is assumed that the packets are so-called IP packets (for the Internet) which have an IP address. The look-up of next-hop information corresponding to the IP address of an incoming packet is controlled by the control means 2 which, in this exemplary embodiment, simultaneously initiate a traversal of the digital search tree (trie) 5 in the router storage means 3 and a look-up in the index cache 4. If one of the rows in cache 4 contain the relevant IP address, a successful lookup has already been performed in trie 5 (recent).

It is then possible to interrupt the traversal of trie 5. Using the index corresponding to the relevant IP address in the cache 4, the information contained in the leaf can be retrieved directly from trie 5. 10 15 20 25 30 516 703 10 If however, there is no such line corresponding to the trie 5.

The index to the leaf relevant IP address, continues the traversing of The traversing ends when the leaf has been found. (which is contained in a leaf's parent node) is stored together with the incoming IP address in the cache 4, preferably by replacing the least recently used line (address) in the cache.

Successful traversal of the digital search tree requires at least one memory access. Since. the memory, here router storage means 3, is assumed to be much slower than the cache, a single file access requires more cycles than a lookup in the cache 4. A successful lookup in the cache 4 therefore results. that the total time counted in cycles to find the desired next-jump information will be significantly reduced.

In general, one ndnnesaccess is not enough to find a leaf in the tree, but it requires several memory accesses.

Fig. 2 very schematically illustrates a digital search tree or a trie 5 'with a number of nodes 1, 2,3,4 and a leaf 5. The figure also illustrates that the nodes and the leaf in trie 5' can be stored in cache 4 'in a way which is independent of the position, ie node 1 stored at the top followed by node 3 while the leaf is stored in the middle followed by nodes 4 and 2 respectively corresponding to memory locations mh qnh. a trie can Fig. 3 is a schematic illustration of how to traverse. "Trie" comes from "retrieval" and it includes a binary, digital search tree in which the bit pattern for the addresses is traversed and in which one or more bits give which child to a given node to select to get to the end node, or the leaf. Fig. 3 shows how, starting from the top of the tree and by examining the bits contained in the IP address from left to right in each node, either route 0 or route 1 down in the tree is selected. When a node that has no sub-nodes 10 15 20 25 30 516 703 .nu o; 11 is examined if the rest of the IP- If this is the case, the path to it It is assumed here that the IP address is 0010. has been reached, also denoted a leaf, the address is in the leaf. correct leaf found.

Fig. 4 shows an embodiment of the invention comprising a device 20 in which packets received via network interfaces NIC1, m, NICm, l1, m, lm correspond to the input port with the same number. An incoming packet with address x is submitted via data buses to control means 22 which includes a search engine, 26A lookup to find the next hop address and exit port (output NIC) is requested.

The search engine 26 then performs a look-up in the cache memory 24 and in the file memory 23 which contains the digital search tree 25. This can be done in series or in parallel. Recently looked up address indexes are located in different places in the cache 24 and they do not need to be sorted so already discussed When the relevant SOIII Above. the information, ie the next jump address and the exit port have been found, either in the cache 24 or in the trien 25, and retrieved, the packet is sent out on the correct NIC. As already discussed above, a look-up in trie 25 is interrupted, if one has been initiated, in the case of a cache hit, ie if the address with the accompanying index to a leaf in the trie has been found in the cache. Alternatively, cache 24 is scanned first and if there is a cache hit, the traverses of trie 25 do not even have to start. However, if there is no cache encounter but the relevant information is only found in trie 25, the index to the leaf in the tri is stored in the cache and advantageously replaces the least recently accessed information or address in the cache.

However, another suitable criterion can also be applied.

In this embodiment, the device implemented in hardware includes an ASIC 21. "on chip". However, "off chip". fully associative cache “on chip” in the ASIC and the access time provided in this case fileinn 23 it would However, the cache is implemented as an alternative could have been arranged fast, 10 15 20 25 30, against i. a routing device, 516 703 o .. n. 12 for a lookup in the cache is much shorter than the time it takes for memory access in trie 25. In alternative embodiments, the cache consists of a direct mapping cache or a "set" associative cache.

Fig. 5 shows another embodiment of the invention consisting of a device 30 in which, like Fig. 4, packets arrive via network interface 11-lm and which are then input via data buses to control means 32. Here too a control means 32 consists of a search engine 26 (or one is responsible for forwarding machine) as the lookups in the file memory 33 and in the cache memory 34. Also in this case the lookups can be done in parallel or in series.

As in the previous figure, the file memory 33 comprises a drive 35. However, in this case the device is implemented as an FPGA (Field Programmable Gate Array) which contains the control means 32 and the cache memory 34. The file memory 33 is provided here "off chip", i.e. it is not on chipet.

In an alternative implementation, not shown, the FPGA chip also contains the file memory. However, a small and inexpensive "on chip" implementation is made possible by keeping the file memory 33 outside the chip 31. I have discussed with reference to Fig. 4. In other respects, the operation is the same as that in Fig. 6, example of a flow, which is a simplified flow chart describing one assumes that a packet (e.g., an IP packet) is taken 1010. cache lookup The IP address is then extracted, 1020, and a l030A, at the same time as a traversal of the triene is initiated, is performed, substantially starting with node 1, lO30B.

After, or even before, access to the first node is completed, it is determined if the address was found in the cache, 1040A. If yes, the index corresponding to the found address is used because 10 '20 25 30' was smaller than the address in the node, 13 find the leaf in the triangle, 1050A. The next-jump information and information about the exit gate are then retrieved from the tri-leaf, l060A.

The packet is then forwarded to the relevant exit port, 107OA. However, if there was no hit in the cache, the triet traversation continues with node n = I1 + 1; n = 1,, p ~ l040B, until the leaf is found (p here simply denotes the leaf). The desired 1050B, 1060B, and the address with the index to the leaf are stored in 10OB. the information is retrieved thereon, the packet is forwarded, as above, the cache, and replaces the least recently used line, Fig. 7 is a flow chart illustrating a traversal of a trie. The figure does not illustrate any previous or parallel flow start, 100, in this case, lookup in the cache. adopted with the receipt of a package of instruments. The address, the IP address, is then provided to the top node in the 110. 120, any match, and the node ie the digital tree structure, in order to then retrieve the node, is examined to see if it is examined whether the searched address is the same as the address in the node , ie if the searched address corresponds to 131, address index in 130. In accordance, the address in the node, the searched information is retrieved from the node, and, in accordance with the invention, the cache is stored, 132. In particular, the address index in the node parent is provided. the leaf in the tree structure. 133, in accordance with relevant next-hop address information to relevant The procedure ceases, although of course it continues with sending packets at the exit port, etc.

However, if it is determined that the searched address did not correspond to the address in the node, it is examined whether the searched address is lower than 140. the child node from the node, the address in the node, If yes, the address is retrieved to the left 141, etc. However, if it is determined that the searched address is not and the left child node is retrieved, 120 it is examined whether the searched address is 10 15 20 25 30 51 s 703 nor n. 14 150. the right child node from the node 151, and the right child node is retrieved, higher than the address in the node, If yes, the address of the 120 is retrieved, and the procedure proceeds as discussed above.

A memory access in the file memory corresponds to step 120. By implementing a cache memory in accordance with the invention, the number of such accesses is significantly reduced.

However, if the entire tree is traversed without finding a matching address in any node, a new tree must be built and this is done in a conventional way. However, when a change occurs The index already of trees in the file memory, the cache must be emptied. is in a cache runs a risk of being incorrect.

Fig. 8 is a flow chart describing address lookup using a cache in addition to the file memory. 200, to the control means in a device according to the invention. The entered all cache memory, 210, to see if there will be any cache hit, 220. If 221, and the 222, 223. however, it is determined that there was no cache hit, performed address, the address is then matched to addresses contained in yes, the searched node is retrieved from the file memory, the searched information is extracted from the node, whereupon the procedure, in terms of memory access, is terminated, If there is a normal file access, 230, as discussed Fig.7. However, Fig. 7 shows a special implementation. It is also possible to build a search engine that runs both feeds simultaneously. If there is a cache hit, the normal flow is interrupted. In case of cache failure, the flow is interrupted as described above because a normal flow is already running. However, when the file entry access 131 has been performed (successfully), the index is stored in the cache, 231, whereupon the flow of memory accesses is terminated, 232. In an alternative implementation, the step of retrieving a node may , information extraction and cache lookup are divided into three pipeline steps and a new lookup can be initiated for each cycle.

Parallel lookups of more than one address can also be performed.

A pipe-line process can also be accomplished in other ways. A single flow can also be provided in the pipe-line in some alternative way.

In addition, the inventive concept can be used in combination with any kind of compressed algorithms, etc. to speed up the traversal of the tri-based structure.

The inventive concept can be implemented to provide Gbyte routers as well as Tbyte routers and it can be implemented for IPv.4 as well as for IPv.6; the principle remains the same. Also in other respects, the invention is not limited to the specifically illustrated embodiments but can be varied in a number of ways within the scope of the appended claims.

Claims (30)

A patent claim (10; 20; 30) by a routing device in a packet-switched network or between networks, A device in for forwarding data packets wherein said routing device comprises a number of input ports, a number of output ports and control means (2), such as a forwarding machine, for controlling address lookup and forwarding of router storage means (3; 23; 33) search trees (5). ; 5 '; 25; 35), the scan of which comprises traversing the tree from packets received over input ports, which includes a digital (trie) root of a leaf through a number of nodes, characterized by (4; 4'; 24 ; 34) number of addresses with corresponding indexes to the leaves for a number that a cache memory is provided for storing a next-hop addresses, and for looking up a next-hop address for an incoming packet, (4; 4 '; 24; 34). a search is performed at least in the cache A device according to claim 1, characterized in that the control means (2) are used to receive incoming addresses, eg IP addresses, and to initiate a look-up of the corresponding next-hop address, comprising one (4; 4 '; 24; 34), if necessary, the digital search tree (5; 5'; 25; 35). cache storage and, a traversal of A device according to claim 1 or 2, characterized in that a traversal of the digital search tree (5; 5 '; 25; 35) is initiated by the look-up in (4; 4'; 24; 34). substantially simultaneously with the cache 10 15 20 25 30 17 A device according to claim 3, characterized in that the traversal of the digital search tree (5; 5 '; 25; 35) is interrupted at a cache hit. A device according to claim 1 or 2, characterized in that the traversal of the digital tree (5; 5 '; 25; 35) is initiated only if the look-up in the cache (4; 4'; 24; 34 ) does not succeed, ie if the address with an index to the next-jump address can not be found. A device according to any one of the preceding claims, characterized in that the indexes of the leaves for a number of the most recently searched next-jump addresses are stored in the cache memory (4; 4 '; 24; 34). A device according to any one of the preceding claims, characterized in that the least recently used addresses in the cache (4; 4 '; 24; 34) are successively replaced by newly entered addresses. An apparatus according to any one of claims 1-6, characterized in that a time interval defined for replacing addresses in (4; 4 '; 24; 34) during such a time interval is replaced by new addresses. cache so that addresses that have not been used A device according to any one of the preceding claims, characterized in that the access time for a cache access is shorter than a memory access in the digital search tree (trie). 10 15 20 25 30 1 -._- u nu -.- 1 'o nu .- o 0'. u ~, _. o 'a no- ucu- I. o n apan n gs16 7o3 18 10. a device according to any one of the preceding claims, that the cache memory (4; 4 '; 24; 34) consists of a direct mapping cache, a “preset” associative cache or a fully associative cache. 11. ll. A device according to any one of the preceding claims, wherein the device is implemented as an ASIC chip. 12. A device according to any one of claims 1-10, wherein the device is implemented as an FPGA chip. 13. A device according to any one of the preceding claims, n n e t e c k n a d where the digital tree structure is arranged on-chip. A device according to any one of claims 1-12, characterized in that the storage means tree structure is provided "off-chip". which are implemented as a digital 15. a device according to any one of the preceding claims, that the cache memory is arranged "on-chip". 16. a device according to any one of the preceding claims, that the device comprises an IP (Internet) router. 17. A device according to any one of the preceding claims, us-o ~ a oocogg 10 15 20 25 30 516 703 19 that the routing table comprising a digital search tree is a compressed data structure. A device according to any one of the preceding claims, characterized in that the digital tree consists of an LC tree, a Patricia tree or any other suitable tree. A device according to any one of the preceding claims, characterized in that a number of addresses are looked up in parallel. A device according to any one of the preceding claims, characterized in that a pipe-line procedure is implemented. A method for routing a packet by routing device in packet-switched data network, wherein said routing device includes a control means (2) and router storage means (3; 3 '; 23; 33) comprising a digital search tree, wherein the method is characterized by the steps of: - storing index to the next-hop addresses for a number of data packet addresses in an associative cache, - use the cache and a traversal of the digital search tree to find an index to the next-jump address or to the leaf that contains the next-jump address , - interrupt the traversal of the digital search tree if there is a cache hit, otherwise - continue traversing the digital search tree until the next jump address is found, - retrieve the next jump address information and forward the packet to the relevant exit port. 10 15 20 25 30 516703 n n .and n. 20 The method of claim 21, characterized in that it comprises: - first performing storage on the cache; onx there will be no cache hit, - initiate a traversal of the digital search tree. The method according to claim 21, characterized in that it comprises: - simultaneous execution of look-up in the cache and initiation of a traversal of the digital search tree, - interrupt the traversal of the digital search tree if it becomes a cache hit, otherwise - continue with traversing until the leaf containing the next-hop address is found. The method of claim 22 or 23, characterized in that it comprises the step of, when a next-hop address is found by traversing the digital search tree, for example by replacing the least recently accessed - stored index said jump address in the cache, the address information if there is no free space. The method of claim 21, characterized in that it comprises the step of: to the address information in the cache with index to the most-replaced index the least recently accessed recently used address information. 10 15 20 25 30 516 703 u n ma »oo 21 The method according to any one of claims 21-25, characterized in that the cache memory is a fully associative cache arranged "on-chip" in an FPGA ASIC used for or an implementation of the routing device. 27. The method of any of claims 21-26, characterized in that a number of next-hop addresses are looked up substantially in parallel. A packet data communication system comprising a plurality of routing devices within a network or interconnecting network, each routing device comprising a plurality of input and output ports; characterized in that in at least a number of routing devices a cache is arranged to store indexes to a number of next-hop addresses contained in the digital search tree, and to find a next-jump address a look-up is performed at least in the cache . A system according to claim 28, characterized in that a traversal of the digital search tree is initiated substantially simultaneously with the look-up in the cache memory and that it is interrupted if there is a cache hit. A system according to claim 28, characterized in that a traversal of the digital search tree is only initiated if there is no cache hit.