SE516467C2 - Method and apparatus for convolution - Google Patents

Description

20 25 30 516 46.7 2.

PRIOR ART The mathematical definition of folding for the current application is shown in Formula 1 below. ya) = lhx 0 where x is input, h is the fold core (fi lter) and y is output.

Modern Signal Processing is based on Fourier transform of current signals in the time plane to transformed signals in the frequency plane. The signal processing then takes place in the frequency plane. The convolution to be performed in the schedule corresponds to multiplication in the frequency schedule. Since multiplication is a simpler operation, previous signal processing has also in this context been implemented through multiplication in fast hardware.

It is then also necessary to transform from the time to the frequency plane and back again. For these operations there are algorithms that are particularly suitable for computers, so-called Fast Fourier Transform (F FT), and its discrete equivalent, with inverses. For a long time, commercially available processors have been tailored for these calculations, so-called digital signal processors (DSP).

A problem with solutions in the frequency plane is that the calculation time for FFT grows unpleasantly with the length of the filter (N * logN). For folds of 100,000 points, this method is unfavorably measured in the amount of hardware compared to performing the calculations in the schedule. A contributing reason is that the calculation of FFT requires calculation with fl integers, while all calculations in the schedule can be performed with integers. One difficulty with scheduling is that there is no known method to continuously perform such calculations in real time. p1000179 ps.doc; ver 4 10 15 20 25 30 516 467 3.

There is also no known device with which the calculations could be performed in real time.

THE INVENTION IN SUMMARY An object of the invention is to provide a method for folding digital signals. This object is achieved by the invention having obtained the features specified in claims 1 and 6, respectively. The invention solves the problem of performing long convulsions of sound in real time with a reasonable amount of hardware.

According to the invention, the basic folding operations are carried out in parallel in an efficient manner. Audio samples from an input signal and terms, or efltercoefficients, from the impulse response are stored in registers. Each sound sample and ko lter coefficient is multiplied separately and in parallel with each other. Then the products are added.

The additions of the products can take place in a so-called adder tree, where the included terms are first added in pairs. The sums are added again in pairs in a repeated sequence until a final sum is calculated. As a result of the Commutative Law of Addition (the order is immaterial), this procedure gives exactly the same result as if the original numbers had been added in turn.

A key question for achieving an efficient calculation is how the data included in the impulse response is to be processed. An impulse response can comprise in the order of 100,000 samples. In order to avoid problems with massive use of hardware, the impulse response is divided into segments according to the uptake. The required hardware is thereby dramatically reduced by the fact that it can be used in a process with time multiplexing.

Furthermore, each segment of the impulse response is used efficiently by performing folding operations with the segment together with fl your samples from the input signal. The calculated results are summed in associated positions in an output buffer, from which the output is output.

Additional advantages and features of the invention are set forth in the following description, drawings, and dependent claims. p1000179 ps.doc; ver 4 10 15 20 25 30 516 467 4.

BRIEF DESCRIPTION OF THE DRAWINGS The invention will now be described in more detail with the aid of exemplary embodiments with reference to the accompanying drawings, in which Fig. 1 Fig. 2 schematically shows an implementation for discrete folding in the schedule, schematically shows an execution of an implementation for discrete folding in the schedule in accordance with the invention, Fig. 3 shows how registers in the embodiment according to Fig. 2 interact during different phases of the folding, Fig. 4 Fig. 5 shows how the contents of registers change during different phases of the folding, schematically shows an implementation of an output buffer, which is used in the embodiment according to Fig. 2, and Fig. 6 shows the function of a calculation unit in the embodiment according to Fig. 2.

THE INVENTION Discrete folding in the schedule can take place in accordance with Formula 2 below. A practical example of implementation is shown in Fig. 1. y (t) = É h (v) x (t - v) (2) where x constitutes input data, h constitutes the folding core (fi lter) and y constitutes output.

The basic operations in folding can be parallelized very effectively. In a first shift register 10, input samples are entered. A corresponding first alter register 18 contains the impulse response. Sound samples and impulse responses are stored in registers 10 and 18, in which each value has its own direct output. A separate unit for p1000179 psdoc is provided for each pair of audio sample and kolterkoef fi cient; ver 4 10 15 20 25 30 516 467 5 ß multiplication, ie all the multiplications are performed in parallel. Fig. 1 shows all the units for multiplication combined in one multiplication unit 12. All the results of these multiplications must then be added, and also this can be performed in a single step in an addition unit 13.

An effective way to organize the addition is to first add the included numbers in pairs. Then you get half as many numbers and can then add these in pairs in a similar way. After a few steps, you have a single number that results. A so-called adder tree is used. As a result of the commutative law of addition (the order is insignificant), it is known that this is exactly the same result as if one had added the original numbers in parallel or in turn. Since the pairwise additions in each step are performed in parallel, the total time becomes the same as for one, ie the total calculation time for the whole adder tree becomes proportional to zlogN instead of to N, where N is the total number of bits of the input numbers.

Without further measures, the delay in the entire calculation chain can still be too long in relation to a certain clock cycle time. This problem can be solved by inserting a number of registers on the road and dividing the calculation into a number of clock cycles. In this way, the clock frequency can increase and still give a result per clock cycle (pipelining).

It is possible to perform the multiplication in a single (combinatorial) step. In doing so, it will limit the clock frequency and it may be sufficient to place a register before and after the multiplier and one inside and one after the adder tree. If an even faster solution is desired, the multiplication must also be divided into fl your pipeline steps.

In the following reasoning, the starting point is an example with the data rate 50kHz for the sound, the clock frequency 50 MHz for the digital electronics (1000 times faster) and a reverberation time of 2 seconds and 16 bit data for both sound and impulse response. An impulse response of 100,000 samples is used. By using such a high clock frequency, it becomes possible to divide the problem into segments and time-multiplex the hardware, ie make the hardware only a thousandths as wide and use it 1000 times instead. The narrow variant p1000179 ps.doc; ver 4 10 15 20 25 30 516 467 6.

The practical structure of a hardware unit in accordance with the invention is shown schematically in Fig. 2. The input data is taken in via an input buffer 14, which is suitably designed as a shift register. The data buffer 14 is connected via a gate circuit 15 to a first register 10. The first register 10 is operatively connected to a second register 11. The first register 10 and the second register are also suitably designed as shift registers. The first register 10 and the second register are fed back via a feedback loop 25 and the gate circuit 15, so that it is possible to shift data back and forth between the registers in a circulating process. The process is described in detail below.

A memory 16 is provided for storing the impulse response. The impulse response is divided into segments and acts as a filter on the input signal. In the embodiment shown, the memory 16 is designed for storing 1000 segments of 100 samples each, or terms. A segment of the impulse response is processed together with a corresponding segment of input data. A first calculation step takes place in a multiplication unit 12. The multiplication unit 12 comprises a number of multiplication means for parallel multiplication of individual samples from the input data signal and from the impulse response. The segment of the impulse response to be processed is transferred via a multiplexer 17 to a first isterlter register 18. The memory 16 is also connected via the multiplexer 17 to a second reglter register 19.

The embodiment shown in Fig. 2 is particularly suitable for pipelining, or logical pipeline. In this case, constituent components, e.g. registers and calculation units, fl your logical blocks, each block performing part of an operation. Several operations in series are thus apparently performed simultaneously.

An alter register is sufficient if the listener's head is completely still. If the listener turns his head, you can use the same echogram, but must calculate new impulse responses. On a modern PC, this can be done in a few tens of milliseconds, fast enough to be able to create a seemingly continuously moving sound image that follows the main rotation in real time.

Correct reproduction even at head rotation can be achieved by doubling the memory for impulse responses in a similar manner as the corresponding buffer p1000179 ps.doc; ver 4 10 15 20 25 30 516 467 7. b ar in the folding unit. While one memory uses constitution, the other is filled with new content. Switching between memories can take place instantaneously.

Consequently, while data from the first alter register 18 is being processed, new alter data from the impulse response can be transferred to the second alter register 19. Data is used and loaded alternately in the two alter registers 18 and 19, so that the processing can take place without delay for loading the registers.

In the embodiment according to Fig. 2 and with a suitable clock frequency of the oscillator which controls the electronics, all hardware will be used at all times during continuous operation. One way to further streamline the solution is to tailor the various calculation units so that not unnecessarily many bits are used in each case. In this way, it is possible to both increase the speed and reduce the amount of hardware.

Each cell of the second shift register 11 and of the filter registers is connected to a single multiplication means of the multiplication unit 12, so that the multiplication can take place in parallel. The result of each multiplication is 32 bits in length, if the included factors are 16 bits in length. Normally, however, only the 11 most significant bits of the result need to be used. It can be even more efficient to tailor the multiplication means, so that they only calculate the pieces needed. In a first step of the addition unit 13, 11 + 11 bits are then used, which in turn gives a result of 12 bits. Thus, the number of pieces is increased by one for each step the adder tree. Depending on the number of steps and the number of segments, only as many pieces are taken as are needed in the end result.

An output 20 of the addition unit 13 is operatively connected to a calculation unit 21. A control unit 22 is operatively connected to the calculation unit 21 and an output data buffer 23. The control unit 22 ensures that the sub-results from the convolution operations available on the output 20 are added to an associated previously calculated and stored partial result in the output data buffer 23. The control unit 22 suitably also controls other components, e.g. the shift registers, the calculation units and the multiplexer. Both the multiplication unit 12 and the addition unit 13 are suitably made in pipeline technology, so-called pipelining. p1000179 ps.doc; ver 4 10 15 20 25 30 516 467 8.

The operation of the circuit of Fig. 2 can be schematically described in the following manner. Audio samples are shifted into the registers, and the various parts of the impulse response are stored in the memory 16 and then loaded into one of the filter registers one part at a time.

The register is doubled, one is loaded while the other is used for folding and then the function is switched (the actual change takes place between two clock cycles and takes no time). Since the output data is then no longer produced at the correct rate, an output buffer 23 is introduced in the form of a memory with a special calculation unit, see the description of Fig. 6 below.

While the filter segment is still in place, folding operations are performed at some point in time (which has already been registered). This is done by means of a three-part input buffer, comprising the input buffer 14 and the shift registers 10 and 11, in which the input data is "swung" back and forth in the two shift registers while new samples are read into the input buffer 14. The results are then superimposed on the correct positions in the output buffer 23 and is eventually fed out at the right rate.

In connection with handling of main rotation, which is schematically described above, a minor modification of the control for the output buffer is also required so that the buffer is reset only when starting with a new sound and not when new impulse responses are loaded. In this way, a "sliding transition" between fi lter for two discrete directions is automatically obtained. It is not necessary to change the filter more often than what corresponds to approximately half the reverberation time, ie in the example described above once per second.

F ig. 3A-3D shows how input data can be used efficiently. In a basic position, shown in Fig. 3A, new input samples are shifted in via an input 24 of the input buffer 14. The contents of the input buffer 14 are then further shifted into the first shift register 10 and the second shift register 11. During the folding operations, the input buffer 14, the first shift register 10 and the second shift register 11 to contain different generations of input data.

During the folding operations, the shift registers are interconnected in the manner shown in Fig. 3B. In this case, the input buffer 14 is separated from the shift registers and no change in register contents is permitted. However, incoming input samples continue to shift into the input buffer 14 as they arrive. p1000179 ps.doc; ver 4 10 15 20 25 30 516 467 Q I While a segment of the impulse response is loaded in one of the filter registers, e.g. the first shift register 18, the input data in the first shift register 10 and the second shift register 11 are "rocked" back and forth until all samples are combined with the impulse response sample in the first shift register 18. and eventually fed out at the right rate. With a solution adapted to the example, all buffers / registers are 100 positions, or samples, long and 16 bits wide and the memory 16 for the impulse response contains 1000 segments. In this way, the folding unit is kept busy every clock cycle once it has started. In the state shown in Fig. 3C, all samples from a segment of the input signal have been used. The data buffer 14 then contains a completely new set, or generation, of input data called G (n). The first shift register 10 contains the most recently used data corresponding to a generation G (n-1) and the second shift register 11 contains even previously used data, corresponding to a generation G (n-2).

Switching then takes place to the state shown in Fig. 3D, in which the contents of the input buffer 14 are transferred to the first shift register 10. This is possible, since the gate circuit 15 has been instructed by the control unit to open for the transfer. The first shift register 10 then contains the generation G (n) data. The data buffer is reset at the same time as preparation for the introduction of new input samples. When entering new data from the input buffer 14 in the first shift register 10, the most recently used data is simultaneously shifted from the first shift register 10 to the second shift register 11, which thereby contains the generation G (n-1) data. Data in the second shift register 11 is not routed into the first shift register 10, since the feedback loop 25 between the second shift register 11 and the first shift register 10 is broken. This can be achieved by the gate circuit 15 breaking the connection. l it in F ig. 3E, the gate circuit 15 has again broken the connection between the input buffer 14 and the first shift register 10, while the feedback loop 25 is closed again. A new series of convolution operations can be started and a new generation of input data G (n + 1) collected in the input buffer 14. p1000179 ps.doc; ver 4 10 15 20 25 516 467 19 I Each convolution gives rise to an output data point and it has been calculated on the basis of a certain position of the forward and recirculating buffer and a certain segment of the impulse response. To indicate the position in the data buffer, the starting point is that 100 new data have just been shifted in, see Fig. 4. This position is called B (0). The next clock pulse gives the position B (1), etc. to B (99). Data is first shifted to the right through the registers, until all data from the first register has been shifted into the second register 11. In each position a folding operation takes place. Then the same data is used again by shifting data in the reverse direction. Due to the "rocking", the next position is B (98). The very first folding thus originates from 1 (0) and B (0). This value is called I (O) B (O). The next value produced is then l (0) B (1) and so on. After | (0) B (99) then comes l (1) B (98).

When all segments of the impulse response have been passed, 100 new samples are shifted in and the process starts again with I (O) B (O). This value must be added to the previously entered l (1) B (0). In order to distinguish the convolution results, a designation for input time must therefore be introduced. The time for the first input buffer is called T (0) and so on. With this addition, the value of the new output point (no. 100) after update becomes T (O) l (1) B (0) + T (1) l (0) B (0). As a result of the "rocking", the passage of time becomes complicated. The calculations can be understood more simply by focusing on the result in the output data buffer 23.

The following designations are introduced: m number of elements in the convolution register, n number of segments in the impulse response memory 00) elements in the output data buffer At the so-called "steady state", ie. when the folding has been going on for a while, the following Formula 3 applies: If = É fl p + f> 1 ß <3) i = 0 where p1000179 psdoc; ver 4 10 15 20 25 30 516 467 11. p = 0, 1, q = aL.WmJ j = p + q When the convolution starts, all values in the output buffer 23 must be reset. As shown in the table above, it takes some time before all the terms for updating each output point are available. It takes more precisely the time that the impulse response is long.

In practice, the output data buffer 23 may be designed as an ordinary RAM memory organized as a ring buffer in accordance with Fig. 5. The ring buffer has an address pointer 26 for start and an address pointer 27 for end. Between start and end, the buffer is reset. A control unit generates the addresses needed for the update to take place in the correct position at all times and for the data to be output correctly. At the same time as a data point is output, it is reset in the ring buffer and thus becomes ready to eventually become the first value in the buffer again.

If the convolution unit produces a result every clock cycle, it becomes necessary to read out an old value during a clock cycle, add a new contribution and write back the result to the output buffer. This can be solved, for example, by designing a RAM circuit, so that two values can be reached at a time.

Between the convolution unit and the memory, there must therefore be a calculation unit that reads, accumulates and writes.

Four additions are performed during a process step. Since the four additions are not evenly distributed over the four clock cycles, at least one buffer register must be created for intermediate storage of convolution results from one clock cycle to another. A practical embodiment of such a calculation unit 21 is shown in Fig. 6. The calculation unit 21 contains two parallel pipelines 28 and 29, which during four clock cycles read and write in two and add in four.

During clock cycle 1, values are transferred from the output memory to buffer register # 1 and buffer register # 2. p1000179 ps.doc; ver 4 10 15 20 25 516 467 12 v i During clock cycle 2, a new result value from the convolution unit is added to the value in the buffer register # 1. Furthermore, a result value from the convolution unit is added to the value in the buffer register # 2. Furthermore, values are transferred from the output memory to buffer register # 3 and buffer register # 4.

During clock cycle 3, the values in buffer register # 1 and buffer register # 2 are transferred to the output data buffer 23. At the same time, a new result value is added from the convolution unit to the value in buffer register # 3 and a corresponding addition is made to the value in buffer register # 4.

During clock cycle 4, the values in the buffer register # 3 and the buffer register # 4 are finally transferred to the output data buffer 23. The common control unit 22 handles these calculations and addresses the memory.

The solution described above presupposes that the Iyssnar's head is completely still. If the listener turns his head, the same echogram can be used, but new impulse responses must be calculated. On a modern PC, this can be done in a few tens of milliseconds, fast enough to be able to create a seemingly continuously moving sound image that follows the main rotation in real time.

A possible addition to handle main rotation is to double the memory 16 for impulse response in a similar way as the corresponding alternator registers 18 and 19 in the convolution unit. While one memory is used for folding, the other is filled with new content. Switching between memories can take place instantaneously, so that folding does not have to be interrupted. A minor modification of the control for the output buffer is required so that the buffer is reset only when starting with a new sound and not when new impulse responses are loaded. In this way, a "smooth transition" between fi lter for two discrete directions is automatically obtained. It is not necessary to change the .lter more often than what corresponds to approximately half the reverberation time, ie in the described example once per second. p1000179 ps.doc; ver 4

Claims (11)

10 15 20 25 30 516 467 13 I 5 PATENT CLAIMS A method of folding a digital input signal, characterized in that digital signals corresponding to an impulse response for at least one edition of a room environment are stored, that samples of the digital input signal are continuously stored, that a time-limited set of samples of the digital input signal is continuously stored. the input signal is delimited from continuously incoming samples, that the digital signals of the impulse response are divided into a segment consisting of coefficients, that convolution operations are repeatedly performed with a segment of the impulse response and the time-limited set of samples of the digital input signal until all segments of the impulse response treated, that the convolution operations are performed by parallel multiplication of the coefficients of the impulse response and the time-limited set of samples of the digital input signal and by repeated pairwise addition of the products to form sub-results and, that sub-results are summed with previously calculated associated sub-results to form of one output sample, whereby the convolution is performed in the schedule. Method according to claim 1, wherein the folding operations are performed by a pipeline method (pipelining). The method of claim 1, wherein the number of coefficients in a segment of the impulse response is equal to the number of samples in the time-limited set of samples of the digital input signal. The method of claim 1, wherein folding operations are repeatedly performed with a first segment of the impulse response while a second segment of the impulse response is prepared for the folding operations. p1000179 ps.doc; ver 4 10 15 20 25 30 The method of claim 1, wherein the sub-results from the convolution operations are stored until all coefficients in all segments of the impulse response have undergone convolution operations. 6. Device for folding a digital input signal, characterized in that a to (a) a memory (16) for storing digital signals corresponding to an impulse response for at least one edition of a room environment is operational. associated with at least a first filter register (18), the memory (16) and the first filter register (18) are divided into a number of segments with a number of cells in each segment, each cell being able to contain a coefficient of the digital signals of the impulse response, a the input buffer (14) is arranged for storing samples of the digital input signal, the input buffer (14) is operatively connected to memory means (10, 11), the memory means (10, 11) is designed for stepwise shifting of data back and forth between cells of the memory means. (10, 11), each cell of the first filter register (18) is connected to a first input of a multiplier means comprising multiplication unit (12) and cells of the memory means (10, 11) are connected to a second input of the multiplication unit (12) for parallel multiplication of the contents of the cells, one output of each multiplication means is connected to inputs of an addition unit (13) for summing the products from the multiplications to a sub-result, an output of the addition unit (13) via a computing unit (21) is operatively connected to an output data buffer (23), the computing unit (21) comprises addition elements, and a control unit (22) is operatively connected to the computing unit (21) and the output data buffer (23) for controlling the computing unit (21) to sum up new sub-results with previously calculated associated sub-results to form an output sample. p1000179 ps.doc; ver 4 10 15 20 516 467 15. b The apparatus of claim 6, wherein the input buffer (14) is operatively connected to a first shift register (10) for transmitting a time-limited set of samples of the digital input signal, and the first shift register (10) is operatively connected to a second shift register (11) for stepwise shifting of data back and forth between cells of the first shift register (10) and the second shift register (11), Device according to claim 6, wherein the multiplication unit (12) is designed to work with pipeline technology (pipelining). Device according to claim 6, wherein the addition unit (13) is designed to work with pipeline technology (pipelining). Device according to claim 6, wherein the memory (16) is operatively connected to a second alternator register (19) for transmitting coefficients therein, and wherein the first alternator register (18) and the second alternator register (19) are alternately operatively connected. with the multiplier (12) and with the memory (16) respectively. The device of claim 6, wherein the memory (16) is doubled to enable uninterrupted folding when changing the impulse response. p1000179 ps.doc; ver 4