SE511144C2 - Method and apparatus for a grounding surface on a circuit board - Google Patents

Method and apparatus for a grounding surface on a circuit board

Info

Publication number
SE511144C2
SE511144C2 SE9704862A SE9704862A SE511144C2 SE 511144 C2 SE511144 C2 SE 511144C2 SE 9704862 A SE9704862 A SE 9704862A SE 9704862 A SE9704862 A SE 9704862A SE 511144 C2 SE511144 C2 SE 511144C2
Authority
SE
Sweden
Prior art keywords
recess
electrically conductive
ground plane
conductive material
circuit board
Prior art date
Application number
SE9704862A
Other languages
Swedish (sv)
Other versions
SE9704862L (en
SE9704862D0 (en
Inventor
Leif Bergstedt
Bo Carlberg
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9704862A priority Critical patent/SE511144C2/en
Publication of SE9704862D0 publication Critical patent/SE9704862D0/en
Priority to PCT/SE1998/002417 priority patent/WO1999033327A1/en
Priority to AU19933/99A priority patent/AU1993399A/en
Publication of SE9704862L publication Critical patent/SE9704862L/en
Publication of SE511144C2 publication Critical patent/SE511144C2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Electromagnetism (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

The invention relates to a method of creating a grounding area on a circuit board, which circuit board comprises a ground plane (60) and also a dielectric substrate (20) located on top of this ground plane (60). The method is characterized by arranging an area (30) of an electrically conductive material on that side of the dielectric substrate (20) which faces away from the ground plane (60), creating a recess (40) in the dielectric material (20), which recess forms a closed contour and connects the area (30) of electrically conductive material to the ground plane (60), and filling the recess (40) with an electrically conductive material (50). The invention also relates to such an arrangement for ground connection on a circuit board.

Description

15 20 25 30 35 511 144 2 Ett problem med denna typ av gemensamma jordningsytor är att via-hålen uppvisar induktanser, vilket gör att via- hålen kommer att fungera som filter vilka filtrerar bort eller dämpar signaler på vissa frekvenser. 15 20 25 30 35 511 144 2 A problem with this type of common ground surfaces is that the via holes have inductances, which means that the via holes will act as filters which filter out or attenuate signals at certain frequencies.

En tidigare känd anordning för att skapa förbättrade egenskaper hos jordanslutningar i ett kretskort redovisas i US 5 401 912. Denna anordning uppvisar en skärm runt ett via-hål. Anordningen förefaller inte kunna ge fullständig skärmning, och förefaller även öka komplexiteten vid tillverkning av kretskortet.A prior art device for creating improved ground connection characteristics in a circuit board is disclosed in US 5,401,912. This device has a screen around a via hole. The device does not appear to be able to provide complete shielding, and also appears to increase the complexity of manufacturing the circuit board.

REDoGöRELsE FÖR UPPFINNINGEN; Det problem som löses enligt uppfinningen är att skapa en jordningsyta på eller i ett kretskort, vilken jordningsyta ger en bättre jordanslutning än tidigare kända lösningar.DESCRIPTION OF THE INVENTION; The problem solved according to the invention is to create a ground surface on or in a circuit board, which ground surface provides a better ground connection than previously known solutions.

Den jordningsyta som skapas enligt uppfinningen utgör, framför allt inom mikrovågsområdet, en väsentligen homogen jordanslutning utan induktanser.The earthing surface created according to the invention constitutes, above all within the microwave range, a substantially homogeneous earth connection without inductances.

Detta problem löses genom att man, utgående från ett kretskort vilket innefattar ett jordplan samt ett ovanpå detta jordplan beläget dielektriskt bärarlager, anordnar en yta av ett elektriskt ledande material i det dielektriska bärarlagret eller på den sida av det dielektriska bärarlagret som är vänd bort från jordplanet. Därefter skapas i nämnda yta av elektriskt ledande material en urtagning vilken bildar en sluten kontur och sträcker sig genon1 det dielektriska materialet ner till jordplanet.This problem is solved by arranging, on the basis of a circuit board which comprises a ground plane and a dielectric carrier layer located on top of this ground plane, a surface of an electrically conductive material in the dielectric carrier layer or on the side of the dielectric carrier layer facing away from the ground plane. . Thereafter, in the said surface of electrically conductive material a recess is created which forms a closed contour and extends through the dielectric material down to the ground plane.

Urtagningen fylls med ett elektriskt ledande material, varigenonxerhålles en kropp av dielektriskt material vilken är helt innesluten av elektriskt ledande material.The recess is filled with an electrically conductive material, whereby a body of dielectric material is maintained which is completely enclosed by electrically conductive material.

För signaler' på. högre frekvensområden, exempelvis inom mikrovägsområdet, kommer nämnda kropp att uppfattas som en 10 15 20 25 30 35 511144 3 homogen kropp av elektriskt ledande material, vilket gör att väsentligen inga induktanser kommer att uppträda.For signals' on. higher frequency ranges, for example within the microway range, said body will be perceived as a homogeneous body of electrically conductive material, which means that substantially no inductances will occur.

BESKRIVNING AV RITNINGARNA: Uppfinningen kommer nedan att beskrivas närmare med hjälp av ett exempel på en föredragen utföringsform, och med hjälp av de bifogade ritningarna, där Fig 1 Schematiskt ovanifrån visar ett utgångsämne för skapande av en jordningsyta enligt uppfinningen, och Fig 2 och 3 schematiskt ovanifrån visar utgångsämnet från fig 1 i senare steg av en metod enligt uppfinningen, och Fig 4 visar en anordning enligt uppfinningen, sedd från sidan, och Fig 5 visar anordningen från fig 3 i snittet V-V.DESCRIPTION OF THE DRAWINGS: The invention will be described in more detail below with the aid of an example of a preferred embodiment, and with the aid of the accompanying drawings, in which Fig. 1 Schematically shows from above a starting material for creating a ground surface according to the invention, and Figs. 2 and 3 schematically from above, the starting material from Fig. 1 shows in later stages of a method according to the invention, and Fig. 4 shows a device according to the invention, seen from the side, and Fig. 5 shows the device from Fig. 3 in the section VV.

FÖREDRAGEN UTFÖRINGSFORM: I fig 1 visas schematiskt ovanifrån ett utgångsämne 10 för skapande av en jordningsyta enligt uppfinningen.PREFERRED EMBODIMENT: Fig. 1 shows schematically from above a starting blank 10 for creating a ground surface according to the invention.

Utgångsämnet 10 innefattar ett jordplan (ej visat), ett ovanpå detta jordplan anordnat lager av ett dielektriskt material 20, samt, en yta 30 av ett elektriskt ledande material, vilken är anordnad ovanpå det dielektriska materialet 20.The starting blank 10 comprises a ground plane (not shown), a layer of a dielectric material 20 arranged on top of this ground plane, and, a surface 30 of an electrically conductive material, which is arranged on top of the dielectric material 20.

Som dielektriskt material kan användas ett organiskt eller oorganiskt material med önskvärda dielektriska egenskaper.An organic or inorganic material with desirable dielectric properties can be used as dielectric material.

Som exempel på oorganiskt material kan nämnas keramiska material, och som exempel på organiskt material kan nämnas teflonmaterial.Examples of inorganic materials are ceramic materials, and examples of organic materials include Teflon materials.

Enligt uppfinningen skapas en sammanhängande urtagning i ytan av elektrisk ledande material, vilken urtagning 10 15 20 25 30 35 511 144 4 sträcker sig genom det dielektriska materialet, ner till jordplanet. Detta visas i fig 2, där utgångsämnet 10 från fig 1 visas med en kvadratisk urtagning 40. Urtagningen kan givetvis ha andra geometriska former, exempelvis en cirkel, men bör bilda en sammanhängande kontur.According to the invention, a continuous recess is created in the surface of electrically conductive material, which recess extends through the dielectric material, down to the ground plane. This is shown in Fig. 2, where the starting blank 10 from Fig. 1 is shown with a square recess 40. The recess can of course have other geometric shapes, for example a circle, but should form a continuous contour.

Urtagningen kan skapas på ett stort antal för fackmannen välkända sätt, vilka inte närmare kommer att skildras här.The recess can be created in a large number of ways well known to those skilled in the art, which will not be described in more detail here.

Som exempel på metoder för att skapa urtagningar kan dock nämnas laser, etsning och mekanisk bearbetning såsom exempelvis fräsning.Examples of methods for creating recesses include laser, etching and mechanical processing such as milling.

Efter det att urtagningen 40 har skapats fylls den med ett elektrisk ledande material 50, vilket visas i fig 3.After the recess 40 has been created, it is filled with an electrically conductive material 50, as shown in Fig. 3.

Eftersom urtagningen bildar en sluten kontur skapas på detta vis en av elektriskt ledande material innesluten kropp av dielektriskt material.Since the recess forms a closed contour, a body of dielectric material enclosed by electrically conductive material is created in this way.

I fig 4, vilken visar det resulterande kretskortet sett från sidan, och i fig 5 vilken visar det resulterande kretskortet sett från sidan, enligt snittlinjen V-V från fig 3, framgår denna kropp 80.In Fig. 4, which shows the resulting circuit board seen from the side, and in Fig. 5, which shows the resulting circuit board seen from the side, according to the section line V-V from Fig. 3, this body 80 is shown.

När urtagningen 40 fylls med elektriskt ledande material 50 sker detta företrädesvis med hjälp av plätering, och det elektriskt ledande materialet 50 är i en föredragen utföringsform koppar. Vad gäller urtagningens 40 dimensioner bör den så kallade "ratio-regeln" följas, vilket innebär att urtagningens bredd minst bör vara samma som urtagningens djup.When the recess 40 is filled with electrically conductive material 50, this is preferably done by means of plating, and the electrically conductive material 50 is in a preferred embodiment copper. With regard to the 40 dimensions of the recess, the so-called "ratio rule" should be followed, which means that the width of the recess should be at least the same as the depth of the recess.

Den kopparinneslutna kropp 80 av dielektriskt material som skapas enligt metoden kommer framför allt av signaler på högre frekvenser, exempelvis mikrovågsområdet, att uppfattas som en homogen kropp av elektriskt ledande material. Detta gör att om kroppen 80 utnyttjas som 10 15 20 511144 5 jordningsyta kommer denna jordningsyta att vara väsentligen fri från induktanser.The copper-enclosed body 80 of dielectric material created according to the method will be perceived above all by signals at higher frequencies, for example the microwave range, as a homogeneous body of electrically conductive material. This means that if the body 80 is used as a ground surface, this ground surface will be substantially free of inductances.

Vad gäller dimensioneringen av ytan 30 av elektriskt ledande material gäller att denna yta bör dimensioneras så att. den i allt väsentligt motsvarar dimensionerna hos stiften, "benen", hos de komponenter 'vilka nan. önskar ansluta till ytan 30.As for the dimensioning of the surface 30 of electrically conductive material, it applies that this surface should be dimensioned so that. it substantially corresponds to the dimensions of the pins, the "legs", of the components' which nan. wishes to connect to the surface 30.

Uppfinningen är inte begränsad till de utföringsformer som har beskrivits ovan, utan kan fritt varieras inom ramen för de efterföljande patentkraven. Exempelvis kan urtagningen och även pläteringen göras med i stort sett godtyckligt valda metoder, om de ovan angivna villkoren för urtagningen respektive pläteringen innehålles.The invention is not limited to the embodiments described above, but can be freely varied within the scope of the appended claims. For example, the recess and also the plating can be done with largely arbitrarily chosen methods, if the above conditions for the recess and plating are included.

Vidare är det fullt tänkbart att pläteringen av urtagningen bara görs i dielektrikat, innan urtagningen och den elektriskt ledande ytan anordnas på dielektrikat. En lämpligt dimensionerad och fylld urtagning, ovanpå vilken anordnas en yta av elektriskt ledande material kommer då att bilda den kropp som har skildrats ovan.Furthermore, it is entirely conceivable that the plating of the recess is only done in dielectrics, before the recess and the electrically conductive surface are arranged on dielectrics. A suitably dimensioned and filled recess, on top of which a surface of electrically conductive material is arranged will then form the body which has been described above.

Claims (11)

10 15 20 25 30 35 511 144 108695 USN 1997-12-19 PATENTKRAV:10 15 20 25 30 35 511 144 108695 USN 1997-12-19 PATENT REQUIREMENTS: 1. Metod för skapande av en jordningsyta på ett kretskort, vilket kretskort innefattar ett jordplan (60) samt ett ovanpå detta jordplan (60) beläget dielektriskt bärarlager (20), vilken metod k ä n n e t e c k n a s d ä r a v att den innefattar följande steg: - på den sida av det dielektriska bärarlagret (20) som är vänd bort från jordplanet (60) anordnas en yta (30) av ett elektriskt ledande material, - i det dielektriska materialet (20) skapas en urtagning (40) vilken bildar en sluten kontur och förbinder ytan (30) av elektriskt ledande material med jordplanet (60), - urtagningen (40) fylls med ett elektriskt ledande material (50).A method for creating a ground surface on a circuit board, which circuit board comprises a ground plane (60) and a dielectric carrier layer (20) located on top of this ground plane (60), which method is characterized in that it comprises the following steps: the side of the dielectric support layer (20) facing away from the ground plane (60) is provided with a surface (30) of an electrically conductive material, - in the dielectric material (20) a recess (40) is created which forms a closed contour and connects the surface (30) of electrically conductive material to the ground plane (60), - the recess (40) is filled with an electrically conductive material (50). 2. Metod enligt krav 1, enligt vilken urtagningen (40) görs med hjälp av laser.Method according to claim 1, according to which the recess (40) is made by means of a laser. 3. Metod enligt krav 1, enligt vilken urtagningen (40) görs med hjälp av etsning.Method according to claim 1, according to which the recess (40) is made by means of etching. 4. Metod enligt krav 1, enligt vilken urtagningen (40) görs med hjälp av mekanisk bearbetning.Method according to claim 1, according to which the recess (40) is made by means of mechanical processing. 5. Metod enligt något av föregående krav, enligt vilken den slutna kontur som urtagningen (40) bildar är en kvadrat.A method according to any one of the preceding claims, according to which the closed contour formed by the recess (40) is a square. 6. Metod enligt något av föregående krav, enligt vilken den slutna kontur som urtagningen (40) bildar är en cirkel. 10 15 20 25 511 144 7A method according to any one of the preceding claims, according to which the closed contour formed by the recess (40) is a circle. 10 15 20 25 511 144 7 7. Metod enligt något av föregående krav, enligt vilken urtagningen (40) görs minst lika bred som urtagningens (40) djup.A method according to any one of the preceding claims, according to which the recess (40) is made at least as wide as the depth of the recess (40). 8. Anordning för jordanslutning på ett kretskort, vilket kretskort innefattar ett jordplan (60) samt ett ovanpå detta jordplan (60) beläget dielektriskt bärarlager (20), k ä n n e t e c k n a d d ä r a v att den innefattar: - en första yta (30) av ett elektriskt ledande material på den sida av det dielektriska bärarlagret (20) som är vänd bort från jordplanet (60), - en med elektriskt ledande material (50) fylld urtagning (40) i det dielektriska materialet (20), vilken urtagning (40) bildar en sluten kontur och förbinder den första ytan (30) av elektriskt ledande material med jordplanet (60).Device for ground connection to a circuit board, which circuit board comprises a ground plane (60) and a dielectric carrier layer (20) located on top of this ground plane (60), characterized in that it comprises: - a first surface (30) of a electrically conductive material on the side of the dielectric support layer (20) facing away from the ground plane (60), - a recess (40) filled with electrically conductive material (50) in the dielectric material (20), which recess (40) forms a closed contour and connects the first surface (30) of electrically conductive material to the ground plane (60). 9. Anordning enligt krav 8, k ä n n e t e c k n a d d ä r a v att den slutna kontur som urtagningen (40) bildar är en kvadratDevice according to claim 8, characterized in that the closed contour formed by the recess (40) is a square 10. Anordning enligt krav 8, k ä n n e t e c k n a d d ä r a v att den slutna kontur som urtagningen (40) bildar är en cirkel.Device according to claim 8, characterized in that the closed contour formed by the recess (40) is a circle. 11. Anordning enligt något av följande krav, k ä n n e t e c k n a d d ä r a v att urtagningens (40) bredd är minst lika stor som dess djup.Device according to one of the following claims, characterized in that the width of the recess (40) is at least as large as its depth.
SE9704862A 1997-12-23 1997-12-23 Method and apparatus for a grounding surface on a circuit board SE511144C2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
SE9704862A SE511144C2 (en) 1997-12-23 1997-12-23 Method and apparatus for a grounding surface on a circuit board
PCT/SE1998/002417 WO1999033327A1 (en) 1997-12-23 1998-12-22 Method and arrangement relating to a grounding area on a circuit board
AU19933/99A AU1993399A (en) 1997-12-23 1998-12-22 Method and arrangement relating to a grounding area on a circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9704862A SE511144C2 (en) 1997-12-23 1997-12-23 Method and apparatus for a grounding surface on a circuit board

Publications (3)

Publication Number Publication Date
SE9704862D0 SE9704862D0 (en) 1997-12-23
SE9704862L SE9704862L (en) 1999-06-24
SE511144C2 true SE511144C2 (en) 1999-08-09

Family

ID=20409564

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9704862A SE511144C2 (en) 1997-12-23 1997-12-23 Method and apparatus for a grounding surface on a circuit board

Country Status (3)

Country Link
AU (1) AU1993399A (en)
SE (1) SE511144C2 (en)
WO (1) WO1999033327A1 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5401912A (en) * 1993-06-07 1995-03-28 St Microwave Corp., Arizona Operations Microwave surface mount package
US5448020A (en) * 1993-12-17 1995-09-05 Pendse; Rajendra D. System and method for forming a controlled impedance flex circuit

Also Published As

Publication number Publication date
WO1999033327A1 (en) 1999-07-01
SE9704862L (en) 1999-06-24
AU1993399A (en) 1999-07-12
SE9704862D0 (en) 1997-12-23

Similar Documents

Publication Publication Date Title
US7047628B2 (en) Impedance matching of differential pair signal traces on printed wiring boards
US5023753A (en) Printed circuit
US10834821B2 (en) Electronic circuit module
US7141742B2 (en) Alternating voided areas of anti-pads
US8536464B2 (en) Multilayer substrate
JP2010506380A (en) Multilayer board
WO2001001453A2 (en) Method and apparatus for adjusting electrical characteristics of signal traces in layered circuit boards
JP2017076754A (en) Printed circuit board
US20070137891A1 (en) Passing multiple conductive traces through a thru-hole via in a pcb
CN110506454B (en) Connection structure between substrates
US20060214010A1 (en) Circuitized substrate with shielded signal lines and plated-thru-holes and method of making same, and electrical assembly and information handling system utilizing same
US7348498B2 (en) Partially voided anti-pads
KR100769536B1 (en) Embedded capacitor device having a common coupling area
JPH08242079A (en) Printed circuit assembly
JP2004111967A (en) Electronic packaging with low-resistance high-density signal line, and its manufacturing method
US7129417B2 (en) Method and structures for implementing customizable dielectric printed circuit card traces
US7035082B2 (en) Structure of multi-electrode capacitor and method for manufacturing process of the same
KR100560571B1 (en) Interconnect
US20130299225A1 (en) Via Structure for Multi-Gigahertz Signaling
SE511144C2 (en) Method and apparatus for a grounding surface on a circuit board
JP2007189042A (en) Semiconductor device
JP2015144165A (en) Circuit module and manufacturing method thereof
US10667385B2 (en) Impedance control using anti-pad geometries
US5496971A (en) Circuit arrangement for multilayer printed circuit board
JP6744034B1 (en) Through hole vias and circuit boards

Legal Events

Date Code Title Description
NUG Patent has lapsed

Ref document number: 9704862-3

Format of ref document f/p: F