SE511081C2 - forward-type inverter - Google Patents

Abstract

The invention relates to a forward converter comprising: a transformer (1) through which power is transferred from the primary circuit of the converter to the secondary circuit thereof, a control circuit (IC) for generating a first control signal and controlling the output voltage of the converter, a first switching means (S1) for interrupting the primary winding of the transformer (1) in response to the first control signal, an element (L) for storing energy, a second switching means (S2) synchronized with the first switching means (S1) in such a manner that the switches (S1, S2) are simultaneously in a conducting and, correspondingly, in a non-conducting state, a third switching means (S3) synchronized with the first switching means (S1) in such a manner that the switches (S1, S3) are alternately in a conducting and, correspondingly, in a non-conducting state. To provide simple control, the converter comprises converter means (2, 3, 4) for controlling the second (S2) and the third (S3) switching means responsive to the first control signal generated by the control circuit (IC), whereby the power required for controlling the switching means (S2, S3) is derived from the first control signal generated by the control circuit (IC).

Description

511 081 2 leading / non-leading), but that momentary exceptions may occur in connection with the change of permit.

The invention relates in particular to a converter intended to generate low voltages of less than 5V and extensive synchronous rectification. Converters where synchronous rectification is used can be broadly divided into two main groups: control-driven and self-driven. The present invention relates to the first main group, i.e. control-driven forward-counters.

A known forward converter in continuous mode is controlled by a transistor connection arranged in the primary circuit and two transistor connections arranged in the secondary circuit.

The circuit solution in question comprises a control circuit for regulating the converter output voltage. The control circuit keeps the output voltage at the desired level by using pulse width modulation (PWM), ie. between the lengths of the ON and OFF periods in the converter's trangenonl regulation 'of the ratio of last connections.

It is extremely important for the operation of a forward converter in continuous mode that the transistor connections in the converter's secondary circuit are synchronized with each other, so that they are not conductive at any stage at the same time.

Empty. instantaneous simultaneous conductivity can cause incorrect discharge of the energy stored in the winding. In this case, it is highly probable that the level of the secondary voltage deviates significantly from the desired level, whereby at least the efficiency of the converter deviates significantly from the desired one.

The above-mentioned known converter comprises a control unit for controlling the switching transistors of the secondary circuit. The control unit controls the transistors of the secondary circuit independently of the switching transistors of the primary circuit. The power required for the control of the transistors is formed by a separate power source present in the secondary circuit.

The most significant disadvantage of this known solution is that the control voltage of the couplings is complicated and expensive to generate. The object of the present invention is to solve the above-mentioned problems and to provide a forward converter in continuous mode which is simpler and more economical than known solutions. These objects are achieved with a converter according to the invention, which is characterized in that the second and third coupling means of the converter are FET transistors whose gate capacitance is used as a memory, the conversion means controlling said coupling means with control pulses which are substantially narrower than the first of the control circuit generated the control signal.

The invention is based on the idea that the control of the converter according to the invention can be realized in a much simpler and less expensive way than in known solutions when the control pulses in the connections arranged in the converter secondary circuit are generated by the edges of a PWM control signal in the converter control circuit. in addition, the power necessary for the control of the connections is transmitted with the said control pulses. In addition, since the gate capacitance of the coupling means is used as memories, the control pulses can be very narrow, which improves the efficiency of the converter. The most important advantages of the converter according to the invention are thus that a separate converter is not needed in the secondary circuit to control the connections of the secondary circuit, that the secondary circuit can be controlled in a much simpler and more economical way than in known solutions, and that the efficiency of the converter according to the invention is slightly improved.

The preferred. the embodiments of the converter according to the invention appear from the appended dependent claims 2 - 4.

In the following, the invention will be described in more detail by means of a first preferred embodiment with reference to the accompanying drawings, in which Figure 1 illustrates a forward converter according to the invention, and Figures 2A - 2F illustrate voltages present in the one shown in Figure 1. convert.

Figure 1 illustrates in a general way the coupling in a forward converter according to the invention. The PWM control circuit is arranged on the side of the primary voltages. The converter shown in Figure 1 is used in continuous mode, which means that the energy stored in winding IJ is not fully discharged during the OFF state of the coupling S1.

The converter comprises, in a manner known per se, a main transformer 1, via which power is transmitted from the primary circuit to the secondary circuit. The primary circuit further comprises a coupling S1, which can be e.g. a power MOSFET or a bipolar transistor. The coupling S1, whose drain electrode is connected to a pole of the primary winding of the transformer 1, and whose source electrode is connected to the negative pole of the input voltage Uin, is used to break the primary voltage passing through the primary winding. The input voltage of the converter shown in Figure 1 may vary depending on the application. In telecommunication devices e.g. it is preferably about + 4OV - about + 7OV.

The output voltage of the converter shown in Figure 1 is controlled by a control circuit IC which, by regulating the operating cycle of transistors S1, S2 and S3, generates the desired output voltage for the converter, which in the case of Figure 1 is + 3.3V. The output voltage is regulated by means of pulse width modulation (PWM), ie. by regulating the relationship between the length of the ON and OFF periods. For this purpose, the control circuit IC comprises, in addition to other components, an oscillator (not shown).

The control circuit IC controls the output voltage on the basis of voltage information and primary current information obtained from the converter output. The output voltage information is provided by a differentiating amplifier 6 with galvanic isolation. The differentiation amplifier 6 supplies the output voltage information to the input circuit Vfb. Information 511 081 about the primary current is taken from the primary circuit by means of a current measuring transformer 5, and is supplied to the current measuring input Is of the control circuit. In the example in Figure 1, the operating voltage Vc of the control circuit IC is taken from the input of the converter.

An encoder Cin is arranged in connection with the input of the converter in a manner known per se.

The converter shown in Figure 1 comprises a transformer 1, through which power is transferred from the converter's primary circuit to the secondary circuit. The secondary circuit comprises a winding, ie. an output choke L, in which the energy is alternately stored during use of the converter, and from which the stored energy is discharged. The secondary circuit further comprises a second S2 and a third S3 coupling means, and an output capacitor Cout. The connections S2 and S3 in the secondary circuit are FET transistors.

When the converter shown in Figure 1 is used, the couplings S1 and S2 are simultaneously conductive, while the coupling S3 is non-conductive. In this case, the power transmitted via the transformer 1 from the primary circuit to the secondary circuit is divided in such a way that a part of it charges the winding L, while a part is transmitted to a load connected to the output of the converter. When the connections S1 and S2 become non-conductive, and the connection S3 becomes conductive, the energy stored in the winding L is discharged via the connection S3 to the load connected to the output of the converter. Since the winding L is dimensioned to continuously supply current, it supplies current to the load until the first control pulse changes its state from logic 0 level to logic 1 level.

Regarding the function of the converter shown in Figure 1 and in particular its efficiency, it is extremely important that the connections S2 and S3 are not conductive at the same time. According to the invention, the control of the connections S2 and S3 is therefore based on the first control signal obtained from the output of the control circuit IC PWM; by means of this control signal, the control circuit controls the transistor connection S1, which breaks the primary circuit.

The first control signal obtained from the PWM output is led to the control output of the coupling S1 and also to a converter 2. The converter 2 generates narrow control pulses based on the first control signal to the FET transistors S2 and S3 via blocks 3 and 4. On the leading edge of the first control signal feeds the converter. 2 a positive voltage to the input of block 3, and a negative voltage to the input of block 4. In a corresponding manner, the converter 2 supplies a negative voltage to the input edge of the first control signal to the input of the block 3, and a positive voltage to the input of the block 4.

In Figure 1, the transducer block 2 is provided with a graphic symbol of a transformer to illustrate that the blocks 3 and 4 are galvanically isolated from the control circuit by means of the transducer 2, and that the secondary winding belonging to the blocks 3 and 4 is of different polarity.

The same pulse that is fed to block 3 is thus also fed to block 4, but in an inverted form.

The structure and function of blocks 3 and 4 are completely identical. Blocks 3 and 4 can preferably be realized by means of a logic which, in addition to other components, comprises an FET transistor and a diode, which is shown in Figure 1.

For example. during a positive ON pulse applied to block 3, the gate charge of the FET transistor S4 is discharged, whereby the transistor S4 becomes non-conductive. At the same time, a positive charge is formed at the gate of the FET transistor S2; the charge is stored in the memory because there is no discharge path.

The FET transistor S2 therefore remains conductive even if the control pulse generated by the converter 2 returns to the O level, i.e. the charge is stored in memory. When the converter 2 supplies a negative OFF control pulse to the block 3, the control pulse is inverted positively by means of logic existing in the block 3. The FET transistor S4 is thus made conductive, discharging the gate charge of the FET transistor S2, and the transistor S2 becomes non-conductive.

The original control signal IC of the control circuit is thus generated at the gate of the transistor S2, and said first control signal is formed in an inverted shape at the gate of the transistor S3. The term 'inverted' refers herein to replacing the logic 1 level with the logic O level and vice versa. However, the structure of blocks 3 and 4 is preferably such that the control pulses which make the FET transistors conductive are somewhat delayed, while the discharge takes place without delays. Such a structure ensures that the transistors S2 and S3 cannot be simultaneously conducting, not even momentarily.

Because they are in the converter's secondary circuit as synchronous. The rectifier-functioning FET transistors are controlled by narrow control pulses formed by a PWM control pulse, and since the power needed to control the FET transistors is also transmitted by control pulses, it is not necessary to have a separate power source for controlling the FET. - the function of the transistors as synchronous rectifiers.

Figures 2A - 2F illustrate voltages present in the converter shown in Figure 1. Figure 2A shows a PWM control pulse generated by the control circuit IC, i.e. the first control signal. Figure 2B shows a narrow control pulse generated by the converter 2 in response to the PWM control pulse and fed to block 3 by the converter 2. Figure 2C shows a narrow control pulse generated by the converter 2 in response to the PWM control pulse and fed by the converter 2 to block from Figures 2B and 2C it can be seen that the converter 2 supplies to the block 4 the same pulse as to the block 3, but in inverted form. Figure 2D shows a control pulse supplied to the transistor S1 which breaks the primary circuit of the converter; the control pulse corresponds to the PWM pulse. Figure 2E shows a pulse supplied by the block 3 to the gate of the FET transistor S2; the control pulse corresponds to the PWM pulse. Figure 2F shows a pulse supplied by the block 4 to the gate of the FET transistor S3; the pulse corresponds to the inverted PWM control pulse.

It should be understood that the figures described above and the accompanying figures are only intended to illustrate the invention. Those skilled in the art will appreciate that the invention may be modified and modified in various ways within the scope of the invention, which is defined by the appended claims.

Claims (4)

10 15 20 25 30 35 511 081 9 Patent claims 1. Forward converter i. Continuous nxxi comprising: a transformer (1) having a primary and a secondary winding and by which power is transferred from the primary circuit of the converter to its secondary circuit, a control circuit (IC) for controlling the output voltage of the converter by means of of a first control signal generated by the control circuit by using pulse width modulation, a first switching means (S1) arranged at the primary circuit for interrupting the current passing through the primary winding of the transformer (1) in response to the first control signal, an element arranged in the secondary circuit (L ) for storing energy, a second coupling means (S2) arranged in the secondary circuit which is synchronized with the first coupling means (S1) in such a way that said couplings (S1, S2) are located substantially simultaneously in a conductive and non-conductive state, a third coupling means (S3) arranged in the secondary circuit which is synchronized with the first coupling means (S1) in such a way that said couplings (S1, S3) are substantially alternately in a conductive and non-conductive state, respectively, and conversion means (2, 3, 4) for controlling the second (S2) and the third (S3) coupling means in response on the first control signal generated by the control circuit (IC), the effect necessary for controlling said connections (S2, S3) being formed by the first control signal generated by the control circuit “1IC”, characterized in that the t. second (S2) and third (S3) coupling means are FET transistors whose gate capacitance is used as a memory, the conversion means (2, 3, 4) controlling said coupling means (S2, S3) with control pulses which is substantially narrower than the first control signal generated by the control circuit (IC). Converter according to claim 1, characterized in that the conversion means (2, 3, 4) are arranged to supply narrow control pulses to the gate interface of the second (S2) and the third (S3) coupling means in response to the leading edge of the first control pulse, wherein the gate interface of the second coupling means (S2) remains charged, and the gate interface of the third coupling means (S3) is discharged, and the conversion means (2, 3, 4) are arranged to supply narrow control pulses to the second (S2) and the third (S3). ) the gate interface of the coupling means in response to the trailing edge of the first control pulse, the gate interface of the third coupling means (S3) remaining charged, and the gate interface of the second coupling means (S2) being discharged. Converter according to claim 1 or 2, characterized in that the converter comprises means (5) for supplying to the control circuit (IC) current information (Is) which is based on the current in the primary circuit of the converter. Converter according to one of Claims 1 to 3, characterized in that it comprises means (6) for supplying voltage information (Vfb) to the control circuit (IC) which is based on the output voltage of the converter.