SE446152B - Implantable, tissue-stimulating prosthesis in particular for the cochlea - Google Patents

Abstract

Implantable, tissue-stimulating prosthesis, in particular for the cochlea, that can not only be produced in the form of a single integrated circuit, but also allows great flexibility as regards stimulation techniques and forms of data transfer. Only sixteen electrodes (E1-E16) are required for the stimulation of fifteen different spots (1-15). Each spot (1-15) is stimulated by means of a two-phase pulse controlled by two adjacent electrodes (E1-E16) whose polarity is reversed in the middle of each stimulation period. Even if a type of pulse width modulation is required for the transfer, the exact form for the type can be varied to accommodate completely different stimulation techniques. For example, a single spot (1-15) only can be stimulated during each transfer time interval or several spots can be stimulated during the same time interval. Even if only one spot can be stimulated at a point in time, the system works with such rapidity that simultaneous stimulations of the spots are registered. The system is dimensioned for minimal power consumption and works safely as regards faults so that no one spot can be stimulated longer than a predetermined time period.<IMAGE>

Description

10 15 20 25 30 35 40 82Û403Û ~ 4 2 The research work carried out so far has given rise to certain requirements in addition to the above, which must be met by each practical ear auger prosthesis. About 15 electrode locations must stimulated independently to reproduce an sufficient range of sounds to be able to comprehend speech. It is almost never necessary to stimulate all places simultaneously poem. According to current speech processing techniques in fact, only one or two sites are stimulated at each your time. Stimulation of two or more places at the same time results in effects with regard to additions and reductions of charge, which complicates the stimulation pattern and does so more difficult to develop effective speech processing techniques. Attempt has shown that there is little or no difference of opinion _between stimulation of several places simultaneously or in consequence, but all of which occur within a short period of time of less than 1 millisecond. Whatever differences may occur can be compensated according to the speech processing technology used. When the stimulation frequency is increased beyond 300-500 Hz, is also available slight difference in perception, with this phenomenon probably separately to the maximum reaction rate of nerve fibers.

In view of the above, according to the invention, essential benefits by a prosthesis of the kind mentioned at the outset presents the features specified in the characterizing part of claim 1.

There are several parameters for electrical stimulation, which can 'changes to change the perceived pitch and volume.

In addition to the location of the cochlea, i.e. that of the various electrode The places where energy is supplied are two of the most important meters of pulse repetition rate and pulse energy. Location, has- The performance and energy parameters are interdependent to some extent extent and can be influenced among themselves to construct different sensations. One of the difficulties in determining the risk audibility stimulation parameters are in the large range that of stimulation thresholds and that of highly compressed electrical dynamic range. Stimulation thresholds (the pulse required to perceive a sound) varies in if a range of 30-40 dB not only from patient to patient but even from electrode to electrode for each patent. At the same time, a comparatively small energy increase of only 6 dB give rise to a change in perceived intensity site of 60 dB, this intensity êV'5Û dß being the Range 10 15 20 25 30 35 40 3 8204030-4 from approximately just noticeable to unpleasant on intensity tetsskalan. This means that within the entire stimulation energy the area is the special area of each particular electrode comparatively small but can be anywhere within a total wide area. Because the dynamic areas are too different electrodes can be widely separated within the total energy stimulation area, the prosthesis must have a very high resolution ability. An implantable auditory nerve stimulator is a must provide a large range of pulse energies while it has the ability to control a useful number of perceived intensities for each particular electrode within a small range advice of pulse energies.

The implanted device must have built-in safety thereby, that it must prevent the possibility of too high stimulation, which would otherwise damage sensitive nerves endings. It has also been established that the pulses should be biphasic to reduce electrochemical effects to a minimum, which would result from charge imbalance at _ any electrode point. At each stimulation site, one should first pulse occur, followed by a second similar pulse with opposite polarity. Through stimulation in two phases, electrolytic and bioelectric effects are combined into one minimum, e.g. gas evolution, electrode dissolution and bone growth.

The invention does not relate to speech processing techniques and nor to transmitter constructions. A lot of research work is being carried out in this area. The invention relates itself into an implantable prosthesis in itself, but the prosthesis should facilitate the operation of low energy consumption of the the voice processor and the transmitter, ie it should require minimal ï emergency preparedness energy and should enable efficient modes of operation transfer of energy and data. These are desirable properties of each implantable prosthesis regardless of the design of the external processor / transmitter.

One of the most essential requirements for any cochlear prosthesis is that it is extremely reliable, whereby reliable the unit is increased by providing the device with so few components 10 1s- 20 25 30 35 40 8204030-4 4 as possible and in that it preferably comprises only one or at most two integrated circuit boards, reliability increases with decreasing number of circuit connections.

Another advantage with regard to the simplicity of the device is that the size of the unit can be kept to a minimum, in particular if an output capacitor is not required for each electrode as in the present case. Reliability is a lot essential for an implanted cochlea, as it still is is not known, if the electronics unit including the electrodes can removed from a patient without causing permanent damage on the cochlea. While it would be possible to introduce one connectors between implanted electrodes and electronics »Unit, would thereby introduce an additional component, which could be incorrect, not to mention that the connection are notorious for their poor reliability during unfavorable the same conditions, especially with regard to body fluids.

Once the implanted device once functions and is stable in the body, it becomes the patient's aid to perceive sound. The patient must undergo extensive rehabilitation to learn to hear and interpret what is heard, because, although the device should ideally repeat sound, as people with normal hearing hear it, the sound only can approximated via electrical stimulation. It is not yet known about a second implantation after removal of a faulty one device would give a viable result, with the more rehabilitation would probably even be needed in the event of a favorable result. For these reasons, reliability a major task in dimensioning each implantable earworm prosthesis.

Another essential task is to achieve flexibility during Operation. Until the time of determining the most Effective speech processing techniques should have such a prosthesis enable variations in stimulation sequence.

The prosthesis according to the invention is dimensioned to meet all the above requirements. The embodiment shown of the invention is a 15 channel receiver -stimulator capable of generating two-phase pulses constant amplitude and variable width with such frequency, 10 15 20 25 30 35 ' 40 5 8204030-4 that maximum stimulation is achieved at at least three channels within a time slot of 1 millisecond. As noted above, this is perceived as simultaneous activation and exists hardly any need to power feed more than three places at the same time. Energy and data are inductively connected on the same carrier wave, so that only a single coil is required as reception of both energy and data. This in and of itself means known technology and it has been discovered that a single carrier should be used, if simplicity and small dimensions are to be achieved.

The receiver is dimensioned for intermittent operation and need not be operated during silent periods. Speech also contains redundant information to a large extent and many of the The treatment techniques used often result in entering non-stimulating time periods. The device has ability to be quickly activated and deactivated and returned constantly to a reset state, when the supply voltage drops below a preset threshold when the carrier the transmission stops.

One of the most essential measures according to the invention is the method of arranging the electrodes. Only sixteen electrodes required to form fifteen stimulation places or channels. Each channel comprises two phases, of which the first is the negative stimulation gas, during which the selected electrode N becomes negative in relation to it adjacent electrode (N + 1). The second phase or the the positive stimulation phase is the phase during which polar ~ the teat of the same two electrodes are reversed. Under both the phases for each channel are all unselected electrodes in open circuit. At all other times- points and during channel selection zero (reset stand) all electrodes are interconnected. Through co- disconnection of all electrodes, any residual charge at the electrodes and reduces the electrode polarization _tion currents to a minimum. The interconnection of the electrodes take place both at the end of each time slot and at the beginning of the next door to ensure the removal of obtaining residual charge.

This technique of arranging electrodes in pairs does not have any 10 15 120 25 30 35 40 8204030-4 e equivalent in the prior art. According to a prior art, was an electrode group with a common ground electrode outside earwax. This proposal results in broad stimulation due to the unpredictable current paths through the coil.

Another proposal involves interconnecting alternately electrodes such as a common ground. This proposal results E admittedly in that a more localized current flows at low charge levels, but the multiple ground connections give rise to increase current dissipation at high charge levels. One In addition, a significant disadvantage of this proposal is that two times as many electrodes are required for the same number of channels, since there is a ground electrode for each active electrode.

The best known electrode group is perhaps the one which includes takes individually switched bipolar pairs. For each stimulus ring corresponding place there is a corresponding electrode pair and the pulse is applied to the pair in two phases. Admittedly, this entails bipolar stimulation with minimal current dissipation, but for this twice as many electrodes are required as the stimulation places. With the switching technique according to the invention only sixteen electrodes are required for fifteen stimulation places despite the fact, that real bipolar stimulation achieved with minimal current dissipation.

The injection molded electrode carrier has e.g. a length of 20 mm and a diameter varying between 0.5 and 1.5 mm, wherein the individual electrodes are distributed along its length.

Assembly of an electrode group can of course be simplified significantly, if comparatively few electrodes are required.

The reason why electrode connection in this way can be effective is that a maximum of three channels require simultaneous stimulation and that the stimulation is perceived as being simultaneous, if three places are fed in succession within less than 1 billion second. The above-mentioned French patent specification states that consecutive power supply within 2 milliseconds is sufficient.

-Because actual simultaneous energy supply to multiple- electrode locations are thus not required, nothing is required independent electrode pair for each channel. Two adjacent channels can be activated simultaneously (in succession but soon after each other), even if they share a common electrode. 7 8204030-4 Another advantage of sequential stimulation lies therein, that the problem of current summation at adjacent channels avoided, which would otherwise occur if two adjacent lying bipolar pairs are energized simultaneously. In addition, 5, only one supply voltage is required, with two-phase pulses generated between two adjacent electrodes by first switch one negatively relative to the other and then reverse the connections. When using two foods two storage capacitors would be required, 10 _ which would counteract the requirement of small size. Something there is no problem with a suitable supply voltage to a single source according to the invention, since both phases the two-phase pulse is switched via identical P-channel and N-channel switch in series with the electrodes for the two 15 phases.

The information for the receiver stimulator consists of wave eruption. Preferably if not necessarily one is generated pair of eruptions of the same width for each channel, one The outbreak in each pair controls one phase of the two-phase pulse.

The widths of the two pulses for each channel, which should not stimulated, are so short that stimulation is not perceived, while an internal counter is advanced. To select one special stimulation site after activation of the device Therefore, the first N-1 sites with the maximum scan H speed, which enables the internal channel selection counter can count, while any effective stimulation in fact the electrodes are not applied. After the required 2 (N-1) The short carrier eruptions represent the next two Breaking the first and second phases of channel N, thereby the width of both eruptions separately is in the range 1-100 microseconds. This form of pulse width modulation enables maximum resolution, the analogous technology in the present cases are better than digital technology. in 35 The time required to traverse a channel without stimulation of each site, can amount to 6 micro- seconds per phase, the carrier being active for 4 micro- seconds and passive for 2 microseconds. To "jump Therefore, over 12 channels, 12 microseconds and din .-- .. <....-> _ s »-VN -... ïaïå-a-.ï -... fi ...... , .f - ... 10 15 20 25 30 35 40 s2o4oso-4 8 180 microseconds would be required to skip the total league fifteen channels. Such a high speed enables many different options for stimulating the electrodes. If for example assumes that a maximum of 3 sites should be stimulated within one door and no action is taken to close the door, since the last place is stimulated, e.g. throughput of 'all fifteen channels, even about the third and the the last channel that requires stimulation can be channel no. 7. skipping 12 channels requires (12) (12) or 144 micro- seconds, while stimulation of 3 channels requires 600 micro- Ice seconds. About the activation and deactivation times for the door amounts to 50 microseconds each, is required for one time-inefficient technology a length of the door of alone 844 microseconds, which is a sufficiently short length for to enable the three selected sites to be stimulated "together early ". When applied to an integrated circuit would to and with less than 12 microseconds required to jump over a canal due to the increased speeds, which would be possible.

It is of interest, that the stimulation threshold with very short pulses in fact increase, when the two phases of a pulse are very close to each other. During the run and skipping within non-selected channels, the two phases are separated by only 2 microseconds. This ensures further, that the short pulses for each channel, which should skipped, does not result in noticeable stimulation, because the stimulation threshold is higher than usual, when both the pulses in each pair are close together.

Whether only one or more sites are stimulated effectively during each time slot, carrier transmission may cease or the device is otherwise reset immediately after that that the last place intended for stimulation is affected instead of continuing to let the work process continue put through the entire last channel. This would allow, »That another gap may begin immediately if required.

When the carrier transmission ceases, the device is reset automatically and idling in channel 0, as will to be described below, at which time no places 10 15 20 25 ' 30 35 40 9 8204030-4 stimulated and instead all electrodes are connected, until the stored energy has been consumed, if it is consumed before the start of the transmission of a new information slot. To as a result of this technology, great flexibility is achieved thereby, that the stimulation technique can be determined entirely by _the external data processor. The implanted device makes several different stimulation techniques impossible, ie. complete large or partial 15-channel slots and stimulation of one single place or several places per hatch.

As important as carrier termination is its transmission without interruption, Continuous carrier transmission without information interruption is interpreted as a reset signal. About something error exists in the transmission system, it becomes this way not possible to supply a continuous excessively high current an electrode. Continuous carrier detection results in selection of channel 0 and short circuit of all electrodes.

The device has extra flexibility, because the space between pulses in each pair is simply a function of the width of the carrier interruption. It's just as easy to adjust the delay between phases as it is to adjust phase width. This would not be the case when the generator for two-phase pulses are only controlled inside the prosthesis itself.

The conventional prior art proposal to dimension a multi-channel stimulation device without ï taking into account special stimulation measures is that encode the pacing parameters and applicable electrode address to a binary word, to send the binary information, to decode them in the receiver to re-establish the address and the stimulation parameters and convert the digitally encoded ones the parameter values to an analog charge level and output applicable charge to the addressed electrode. This principle has been applied and works, but this requires one considerable number of components not only in the external system but also in the implanted prosthesis. The number of charge levels, which can be accurately output, depend on the number of bits, which was used to encode the charge level and this depends in its turn on the construction of and the accuracy of the circuits for 10 15 20 25 30 35 40 8204030-4 1 ° digital-to-analog conversion. According to the principle of the invention on the other hand, the theoretical pulse width resolution goes to about 0.33 microseconds, i.e. a period in the carrier used with the frequency 3 MHz, within 100 microseconds, which is equivalent to about 300 discrete levels, despite the circumstance, that the connection itself is comparatively simple. Pulse width determined solely by the external system and any intermediate horizontal analog-to-digital and digital-to-analog conversion is not located. Resolution in energy delivery is very important due to the large range of stimulation thresholds. The one electrode can e.g. have a threshold width of 10 micro- seconds, in which case the threshold for discomfort would be approx 20 microseconds. In the device according to the invention, therefore 30 levels between 10 microseconds and 20 microseconds dissolved, although probably not more than sixteen levels in in fact, are useful. About the threshold and discomfort levels 7 amounts to 50 microseconds and 100 microseconds, respectively, 150 levels can be resolved, a number that is considerable higher than necessary. In all cases, it is trivial too the external system to set the step size (resolution for each stimulation site.

The invention is described in more detail below with reference to the following drawing, in which Figs. 1 and 2 show an embodiment of the invention, with Fig. 1 placed to the left of Fig. 2, Fig. 3 is a timing chart for illustration the operation of the device shown in Figs. 1 and 2, Fig. 4 the components of the decoder shown in Fig. 2 of 4 bits to 16 wires, Figs. 5A-5C the components of the output stages, which are shown in symbolic form at the bottom of Fig. 2, and Fig. 6 shows two alternative transmission schemes which can be used. turned at the device according to Figs. 1 and 2.

The data / energy carrier consists of a series of close to each other horizontal high frequency outbreaks. The sensing coil L1 i Fig. 1 is tuned to the transmitter frequency by means of a capacitor. tor C1. In the illustrated embodiment of the invention a wave frequency of 3 MHz was used. The resonance circuit is low (about 3) to achieve critical tuning and to minimize rise and fall times 10_ 15 20 25 gso 35 40 H 82Û4Û3Û'4 for the peak voltage across the resonant circuit depending on the mode for outbreak transmission. A separation unit 10 for distinguish between information and energy can be designed on 'every known way. In its simplest form, the device consists of one full-wave bridge rectifier for energy supply to the logic by generating a voltage across capacitor C2, which serves to filter the voltage from the rectifier coupling.

A voltage regulator 12 generates a voltage within the range 3-4 volts for power supply of the device. The excitement is over capacitor C2 normally varies with coil spacing and loading, so that the voltage regulator must ensure scratchable and predictable charge delivery to the electrodes.

The voltage regulator itself can be of a conventional type, for example shunt or series type.

Two half-wave rectifiers are also included in the unit 10 for demodulate the carrier signal and generate direct envelope input formation, which is supplied with two tilting steps ST1 and ST2 of Schmitt type. The signal supplied to the ST1 switching stage was turned to pulse control the counter, when the device runs through the 16 channels, namely the reset channel 0 and the active channels 1-15. One resistor R1 and one capacitor C3 determines the rise and fall times and the signal wave at the input of the rocker stage ST1, their values depends on the range of pulse widths in the transmitted signal. The second half-wave rectifier included in the unit 10 was used for to charge the capacitor C4 via a resistor R2. The same orderly logic constitutes a precautionary measure, which prevents, that the device stimulates one of the outputs in it unlikely cases, where the external transmitter generates a conti- modern high-frequency carrier without any data interruptions. This would be a problem if it occurred during a channel scanning process, when one of the active channels is streamed, or if the receiver counter described below calculates incorrectly and any channel other than channel 0 was represented by the state at a time when channel 0 would be represented. In such an erroneous condition would it may not be desirable to supply a continuous direct current any of the electrodes. Despite the fact that the ex- The transmitter in almost all cases would be equipped 10 15 20 25 30 35 40 8204030-4 _ 12 with its own safety coupling to monitor its to prevent the occurrence of such a condition, is it is still desirable for the implanted device has built-in security devices. in the presence of a high frequency carrier, the capacitor is charged C4 via the resistor R2 to the switching threshold for the rocker stage ST2. When the capacitor is charged to the flip-flop threshold step, its output without data gets high level of control of the counter reset and selection of channel 0, such as described below. As long as information is transmitted, follow the output signal from the toggle stage ST1 of the carrier envelope (data signal), as shown in the figure. Each pulse in a channel pair is stands for a rising edge, followed by a falling edge. When there is an interruption in the carrier transmission, ie. data transmitted as a result of detecting the end of a pulse, j. receives the output signal from the rocker stage ST1 low level and the output signal from the inverter 14 high level. This brings the transistor FET1 to conduct and discharge capacitor C4. As long as the carrier is not transmitted continuously long enough for charging capacitor C4 to the trip level of the ST2 rocker stage, the output signal without data from the toggle stage ST2 remains at a low level. Immediately after the capacitor C4 starts charging at the beginning of a data pulse, it is discharged in the event of a data interruption at the end of the pulse, "when the transistor FET1 becomes conductive. Only if the carrier carried continuously for longer than the time TMAX seconds in Fig. 3, the output signal without data reaches a high level. Since in in this case the maximum data pulse width is 100 microseconds, the component values should be selected accordingly way, that TMAX is slightly larger than 100 microseconds. Although the unit 10 is shown to include two half-wave rectifiers for generating separate input signals for the ST1 and ST2 toggle stages, it may be sufficient to use only one rectifier.

Since short rise time is required for capacitor C3, the resistor R2 in this case have such a high value that it has negligible effect on capacitor C3. But it should not be particularly advantageous to use only a single directed in an integrated circuit, especially if discrete 10 15 20 25 30 35 40 13 8204030-4 capacitors are required for capacitors C3 and C4 and integrated capacitances were used instead.

The output signal from the voltage regulator 12 is applied to a supply voltage voltage sensor 16, which detects the level of the supply the tension. The direct output signal from the sensor is high level, as soon as the output signal from the voltage regulator exceeds gives a threshold levelâ, which is higher than the voltage, which in in fact, is required to power the circuit logic. One inverter 18 causes a signal of the opposite polarity appears at its exit.

The first three curves in the time diagram in Fig. 3 show one 'typical data / energy transfer series, the output signal from the voltage the voltage regulator and the output signal from the voltage sensor. The* the original carrier eruption activates the clutch. View the channel from the voltage sensor gets a high level, before the maximum the supply voltage is reached but then a voltage is reached, which in fact can drive the logical elements.

The curve 3D indicates the output signal from the rocker stage ST1, which constitutes data clock pulse signals. With the exception of the original the ridge edge, which is not sharply defined, if stored the energy consumed and the output signal from the voltage regulator must be generated, the data clock pulse signal represents it demodulated carrier. After the initial activation the part of the transmission signals the first data interruption (negative transition), that a couple of pulses are being applied land. As can be seen from curves 3A and 3D, are represented each channel of two pulses of equal width and there is one intervals of 2 microseconds not only between the two phases in each channel pair but also between successive ones pulse pair.

The counter 20 monitors a channel which is in operation. Re- position of the counter to represent channel 0 (safe sign) is controlled by the inverted output the signal without data from gate G6 gets low level. When continuous high frequency received for longer than TMAX seconds, the line for the signal without data has high potential. 10 isf zo f 25 30 35 40 8204030-4- 14 If the input signal ÜÜÜ for the channel 0 to the gate G6 is assumed to have high level, causes the voltage on the non-data line, that the output signal from gate G6 gets low level. Since the di- direct line from the voltage transmitter has high voltage data transfer, the input signal is ïÖïÉ: ÜÃTà to gate G3 gets low level, the output signal from gate G3 gets high level for the reset of both the counter 20 and the flip-flop FF1 (see signals 3E, 3F and 3G) .The by the NON-DATA signal controlled the reset is inhibited if the device is in channel 0 for reasons, which will be explained below, by use of the signal.ÖÉÛ to keep the output signal off gate G6 at high level. The lead for the signal ÖÉÜ is low voltage, when the device is operating with channel 0. Although the counter 20 determines the channel of 16 channels, which is * in operation, each channel has two phases, 'which are determined by tilting FF1. When the rocker stage is reset and its island output has a high level, the device is in phase 2 in a channel.

When the toggle stage is set with its Q output to a high level, the device is in phase 1 in a channel. Since sig- the channel from the output Ö on the rocker stage is fed back to it D-input, triggers successive clock pulses with its rising edge tilts. Outputs Q and Ö are tied with the clock pulse inputs on the first step in the counter 20. As soon as the toggle is triggered to represent phase 1 in a channel, the counter is therefore advanced to represent a new channel.

There are many different transfer principles that can be applied, and it is essential to understand the manner in which the is restored in each case. According to a general special According to the appropriate transmission principle, the carrier frequency was not transmitted between information gaps. This not only saves money energy but also prevents tissue from being continuously set for high frequency radiation, when stimulation in itself the work is not required. Even during speech there are many time periods, as stimulation is not required. In cases where the carrier does not sent between slots, in fact, the end of a gap in that the direct line from the voltage the sensor has a high voltage, as described in more detail below. w 10 15 20 25 30 35 40 15 8204030-4 But this does not mean that insufficient charge is then stored in the capacitor C2 for current supply of the logic elements.

In some cases, even sufficient charge may remain for power supply of the device at the beginning of the next door, if it arrives before the charge in capacitor C2 used noticeably. It is essential that the device synchronized with the next information slot, whether or not satator C2 may or may not have sufficient charge for current feeding the logic immediately at the beginning of the next transmission.

In such operating modes, in which carrier transmission ceases between slots, the required synchronization can be achieved by constantly providing an original carrier crime at the beginning of each gap, the outbreak being sufficiently long to activate the clutch, even if the capacitor C2 may already have sufficient charge to really power the logic. At the end of the original activating the carrier outbreak, the device should be located in channel 0, phase 2, so that after the first data interruption with the rising edge of the information signal on the data corresponding to the beginning of the first data pulse, can set the rocker switch FF1 to the setting state (phase 1) and advancing the counter from representing channel 0 to to represent channel 1.

With regard to the first case, then long enough after the cessation of the carrier transfer exists to achieve, that not only the direct line from the voltage transmitter gets low voltage to indicate the end of a gap but also that the signal from the voltage regulator can decrease to such low value, that the logical elements cannot be operated. It is this case, shown in Fig. 3, the output signal from the voltage regulator according to curve 3B decreases to zero immediately after the output signal from the voltage transmitter according to curve 3C taken low level. As soon as the output signal from the voltage the sensor gets low level at the end of the door, enters the gate G3 i.function, because it is still supplied with energy through the charge remaining in capacitor C2, and receives its utsgnal high level Sat reset of the counter Sat. to represent channel 0 and the toggle step to represent 10- 15 20 25 30 35 40 16 j s204oso-4 ', phase 2. The counter must be reset to channel 0, so that all electrodes are connected in and for charge dissipation ning. Whether the device remains in channel 0 depends on whether the The voltage from the voltage regulator drops to zero before the start of the next door. If so, all synchronization information is lost because the device is not supplied at all any energy, and the device must be re-synchronized with beginning of the next transfer slot. This corresponds to that in Fig. 3 shows the case, whereby the reset pulse at .the end of the signal 3F ends together with the reduction ' of the voltage regulator output signal.

During the activating carrier eruption at the beginning of the next door, the device is synchronized again with channel zero, phase 2.

During the original carrier eruption, the output signal is formed from the voltage regulator eventually, as curve 3B shows.

When it is eventually formed, sufficient voltage is generated for energy supply of the logic, before the voltage is so high, that the direct output line from the voltage sensor receives high voltage. Then the voltage reached sufficient level for energy supply of the logic and next to the direct line from the voltage transmitter receives high voltage, has consequently the output signal from gate G3 high level for resetting of the device in channel 0, phase 2. It can be emphasized here that step FF1 is not clock pulse controlled by means of that on the data line behavior signal. This signal is eventually formed but - when its leading edge is formed, the rocker step is kept reset '_by the reset pulse according to curve 3F. At the time, when the reset pulse ends and the direct line from the voltage sensor reaches a high level, the rocker stage cannot is effectively pulse controlled by the remaining part thereof rising edge of the data clock pulse signal_ The device is consequently reset in channel 0, phase 2, adjacent to one time after the first data interruption. By means of the front edge on the next pulse, namely the beginning of the first data the pulse, the clock pulse is controlled by the rocker stage in such a way that it represents phase 1, while the counter 20 is advanced to represent channel 1. The device is thus placed in channel 1, phase 1 at the beginning of the first data pulse and has experienced poor synchronization achieved. 10 15 20 25 30 35 40 17 8204030-4 On the other hand, it can be assumed that the time between gaps is not sufficient for the output of the voltage regulator should completely disappear. Although the direct management from the voltage sensor gets low level to indicate the end of one gap, therefore, sufficient charge is maintained in the condensate tower C2 between slots for energy supply of the logic. Since this line from the voltage transmitter has low voltage, will the reset output signal from gate G3 to in this case still have a high level. Instead of as shown one short pulse occurs at the end of curve 3F, remains position management at a high level and keep the counter and rocker switch reset in channel 0, phase 2. At the beginning of the next hatch with transmission of the activating carrier eruption has data clock pulse signal with the curve 3D a sharply defined rising edge, which would otherwise clock the tilt, because the logic is still energized and the ST1 toggle follows the incoming data signal and forms a strong one defined pulse leading edge. But the rising edge of data the clock pulse signal appears, while the reset line still has high level. Consequently, it has to the step fed the clock pulse signal did not affect it condition and the rocker stage remains reset to represent phase 2. As soon as the direct line from the voltage the sensor receives a high level, receives the reset output signal from gate G3 was low level, but at this time the data clock pulse line high voltage and it is too late to pulse control tilt. The device is again in channel 0, phase 2, so that the leading edge of the first data pulse after the first data interruption can transfer the device to channel 1, phase 1.

At the second transmission type, which is described below, ceases carrier transmission not between hatches. This allows immediate stimulation control without the need to wait during an activation cycle. In this case, the device is kept restored between gaps in channel 0, phase 1 (not phase 2). Since the the wave is transmitted continuously, the output signal from the voltage remains the high-level regulator as well as the direct line from the voltage sensor. There is a recovery pulse not at all and the device remains in channel 0, phase 1, because 10 1sp 20 25 30 35 40 8204030-4 18 this is where the transmitter left it. After data the interruption, which preceded the placement of the device in duct 0, phase 1, the transmission continues, so that the device is here as soon as it is in channel 0, phase 1.

But for proper synchronization, the device needs something method is transmitted through channel 0, phase 2 to channel 1, phase 1.

For this, it is required in this case that a pulse for channel 0, phase 2 alstras. This is associated with the introduction of a data break in the carrier, which is followed by another card carrier eruption. This outbreak is treated as a data pulse and controls the operation of the device through phase 2 in channel 0.

- After the next data interruption, the leading edge, which enters, the beginning of the first data pulse for channel 1 and the device is clocked to channel 1, phase 1, as usual way.

But in such a case, the circuit for timing control of TMAX can otherwise cause a problem, because in practice is difficult to accurately control the duration of time TMAX. Organizer is expected to remain in the non-stimulating channel 0, phase 1 between gaps in the presence of a continuous carrier wave. If the carrier appears longer than the time TMAX seconds, the NON-DATA line gets a high level. If it was a question of that control a reset, the counter and the toggle would reset to channel 0, phase 2. To avoid such reset and loss in synchronization are included in the input ÜÜÜ on gate G6. If the device is in channel 0, the output signal ÉÉÉÉÜEÃTÃ remains at a high level, even if the -DATA line gets high level to indicate the presence of continuous high frequency, so that any reset pulse not generated.

It is not necessary to engage in excessive stimulation. ring under channel 0, since all electrodes at this time are interconnected. The only time when the safety device against failure is required, is if continuous is present while the device is in any channel other than channel 0. At this time, the time CHO on gate G6 high level and can output 10 15 20 25 30 35 40 19 8204030-4 ÉÉÉÉIÜÃTà is generated for control of reset, about the carrier has a duration longer than TMAX seconds. This type of return position is shown at curves 3E, 3F and 3G. About continuous carrier is assumed to be received while the device is operating in channel 5 (see curve 30), the signal ïÖïÉ: ÖÃTà is generated for resetting, whereby the device is placed in duct 0, phase 2 (the output Q on the toggle stage FF1 has a low level).

The device is so flexible with respect to the type of transmission, that (it enables, intentionally controlled error conditions of this type can in fact be used to separate gaps.

According to Fig. 3, a hatch can be closed simply by transmitting carrying the carrier for TMAX seconds without any data interruption, after which restoration takes place and a work process begins channel 1, phase 1 after the next data interruption. But such a case is not very useful, because the last channel, which used within the cover, must be stimulated for TMAX seconds.

In addition to serving as a filter for energy supply In addition, the capacitor C2 has the task of detect deactivation. As described so far has the signal on the direct line from the voltage transmitter to the task of controlling the reset of the counter at the beginning of each hatch transmission (activation) and at the end of each door transmission (deactivation). Such synchronization is required, if intermittent transmission was used. An information gap was sent only, when stimulation is required, and no transmission does not occur between gaps. A deactivation state is detected of the sensor 16, which determines that the voltage across the capacitor sator C2 decreased below a threshold value. When transmission hear, the capacitor C2 is discharged via some resistance, as then is connected across the outputs of the voltage regulator 12.

The time constant must be such that the capacitor does not discharge charged to the point at which the direct line from the voltage sensor gets low level below the normal interval of 2 microseconds between pulses. Otherwise, activation states are detected all the time. On the other hand the capacitor must not require too long a time for discharge, because an actual deactivation permit would 10 15 20 _25 30 35 40 as2o4o5o-4 v 20 detected as soon as possible, so that the device can reset with all electrodes connected. In order to achieve that the capacitor C2 operates as a reliable one timer, it must be subjected to a load; so that it can be discharged with a predetermined time constant. The lattice G4 and G5 and the function of the transistor FET2 is to switch on the charging resistor R3 in the circuit, so that the capacitor C2 can be discharged via the same and the voltage regulator, when activating time control is required. Such deactivation timing is required as soon as the carrier ceases, e.g. with a data interruption or at the end of one hatch, In this case, the input line ÖÃTÃ gets to the grid G4 high level, so that one entrance of the gate G5 is kept low level. As soon as the carrier transmission stops, the output signal is off sensor 16 is still at a high level, so that the input signal from the voltage sensor for gate G5 also has a low level. When both input signals of the gate have a low level, its output signal has a high level level, the transistor FET2 conducts and the load resistor is connected position R3 in the circuit, so that the capacitor C2 can operate as as a reliable timer. After the time control (in addition to the maximum gap between pulses), gets the direct line from the voltage sensor low level and the gate G3 emits a return position pulse.

Since the device is now restored, it is no longer required continued discharge of capacitor C2. This would not only mean energy loss but would also require longer .time at the beginning of the next capacitor reload slot and to achieve, that the direct management of the voltage transmitter again gets high level. For this reason, from the inverter 18 connected to an input of grinden G5. As soon as the output signal from the sensor 16 reaches a low level and this line gets high level, the transistor FET2 is caused to block, so that any charge remaining in capacitor C2 is not diverted (with the exception of the normally high internal ones the impedances, which may be present in the integrated circuit, on which device is manufactured, and which prevents constant charge storage). While it is not essential that charging remains over the capacitor C2 between gaps, it is desirable, 10 15 20 25 30 35 40 21 82Û403Û "4 that it lasts at least for a short time after the restoration, ie that the voltage remains sufficient high for energy supply to logic. With the device restored, the electrodes are interconnected and would remain interconnected in this way for a sufficiently low time for to enable charge recovery.

Even during scanning of channels 1-15, capacitor C2 as a timer, so that the device can be set and the electrodes are connected if required.

During active channel scanning, they serve connected the electrodes (wherein any pair is energized) such as load resistance. It is only when some are connected electrodes do not exist in which the resistor R3 must be connected the circuit. This occurs during a data interruption between after successive pulse pairs and between the two pulses in each pair, with all electrodes in the open circuit. The input signal ÖÃTÄ to gate G4 has the task to switch on the resistor R3 at such a time. But when the device operates in the channel 0, there are also none interconnected electrodes. In this case, therefore, the state R3 is also switched on in the circuit, so that the time constant C2 / R3 will place the device in phase 2 in channel 0, if it would be in phase 1 of channel O. At this time the line CHO has a high level and feeds the other input on grinden G4. When this input is at a high level, it controls the position of the transistor FET2 to the conducting state is equal to as the high voltage at the input ÜÃTÃ.

So far, the signals controlling the recovery have been described. the counter 20. The counter has 16 states, of which it first controls the interconnection of all electrodes. Where and one of the other fifteen states controls the supply of a two-phase pulse to a corresponding pair of electrodes. That way on which the counter controls the selection of a particular pair of or the interconnection of all these and on which the widths of each pair of electrode pulses are controlled by of a pair of data pulses in the transmitted signal will described below. However, for the description of the it is essential to consider the two further 10 15 20 25 30 35 8204030-4 22 the transmission types discussed above and illustrated in Figs. 6A and 6B.

According to the diagram shown in Fig. 6A, the carrier was not transmitted between hatches and under each hatch only one is stimulated only place. At the end of each hatch, the direct from the voltage sensor is low level and a return is generated. setting pulse, which causes the counter 20 to be reset and represent channel 0 and the toggle stage FF1 to be reset for to represent phase 2.

At the beginning of the next slot, the capacitor C2 may store sufficient charge to activate the logic. But as described above, either leaving the original activating the carrier burst device in channel 0, phase 2, if it has occurred here, ie. the logic is still activated, or it places the device in this same condition through control of a reset, ie. the logic is not activated still. Fig. 6A shows the original carrier output. the crime control the state 0, ø2, ie. channel 0, phase 2.

At the end of the original period of carrier transmission according to Fig. 3A there is a data interruption of 2 microseconds, followed by the leading edge of the first data pulse. With With the rising edge of this pulse, the clock pulse is increased FF1. Because its output Ö, which has a high level below phase 2, is connected to the input D, the output Q now gets high level, while the output Ö gets low level, so that phase 1 now represented. The positive edge of the input signal CK to the counter 20 and the negative edge of the input signal Ö? brings the counter to advance to channel 1. After the first pulse in channel 1 there is a data interruption, followed by it rising edge of the second pulse in channel 1. Toggle step In clock pulse is controlled again, and since the output Ö has low level, it is the output Q that now has a low level and the output Ö which now gets high level. These polarity signals do not progress the counter 20. The counter is again advanced only with it rising edge of the first pulse in the second pair of data pulses. 10 15 20 25 30 35 40 23 8204030-4 As can be seen from curve 3G, the flip-flop FF1 remains placed during the original part of the consignment and becomes the output signal from Q at low level. The original the step on the data clock pulse line clock pulse control does not tilt, as described above. It is only after the original the activation transmission, during which the capacitor C2 is charged, as the toggle clock is controlled at the beginning of it first data pulse. The counter 20 is advanced at the beginning of each pair of data pulses, when the toggle is set to represent phase 1. ' While the device is reset, the ÖÉÜ line has a low level and one input signal is held to each of the gates G1 and G2 at low level. Consequently, both wires are held ÛT and Üï both at high level as shown by curves 3H and 31. But the rocker stage is clockwise with the leading edge on the first data pulse and its output Q have a high level. So as soon as the counter has progressed to channel 1, the output Ü turns on * decoder 22 high level and output ï low level. Neither of the gates G1 and G2 are now deactivated via the line ÜÜÜ.

Gate G2 is still supplied with a low level signal, since the output Ö on the rocker stage has a low level. But the gate G1 is now activated, as its input is connected to the output time Q on the rocker stage, which has a high level. The third input one on each of the gates G1 and G2 are connected to the data line. It is therefore clear that the output signal from gate G1 during the first pulse of the first pair of data Pulses have a low level during the duration of the pulse, which goes off_curve 3H. During the data interruption between two pulses in the first pair has both outputs from gates G1 and G2 high level, because the data line has low level. But the leading edge of the second pulse in the first pair of pulse control the rocker stage again, so that it is now the gate G2, which is activated instead of gate G1. When the data management has a high level, the output signal Ü2 gets low level and maintains this level during the duration of the second pulse in it first pair. Because the two pulses in each pair have ' the same width in the illustrated embodiment of the invention, I shows the first pulse in both signals ÜT and Üï with same width. Both pulses occur when the output signal T is off 10 15 20 25 30 35 40 8204030-4 24 the decoder 22 has a low level, as shown by curve 3K.

When each pair of data pulses arrives, the toggle and the counter is advanced. For each counting state is a special output from the decoder at low level for the duration of the transmitted pulse pair, i.e. from the beginning of the first pulse in the pair to the beginning of the first pulse in the next pair, however the output signals ÉT and ÜÉ have a low level only during the respective pulse of the two pulses. Fig. 3 shown lies the way in which successive places stimulated, depending on the duration of each stimulation on the widths of the two pulses in each pair.

Fig. 6A shows the device in phase 2 of channel 0 at the beginning of the hatch transmission, as described above. At the visual made transmission type are the two pulses in each of channels 1-6 very short. The pulses in Figs. 3 and 6 different width. Although the wires ÉT and fi ï get low level and in fact controls the stimulation of places, the stimulation 'ring so short that it is not perceived. The ineffective the stimuli are indicated in the figure by vertical line segments ment for each of the pulses.

At the beginning of the seventh data pulse pair owns the same type of workflow, when the output 7 of the decoder 22 gets low level, but the two pulses in this pair are wider. According to Fig. 6A, the first pulse is negative and the second positive merely to indicate that the two stimuli are opposite polarity.

In the transmission process according to Fig. 6A, only one is stimulated channel under each hatch and the carrier transmission ceases suddenly at the end of the second, with this channel co- arranged the pulse. The device does not work through channels, which does not require stimulation after the canal, which requires this, when working through channels that do not require stimulation occurs only with respect to the channels, which are lower than the channel, which requires stimulation (in and on behalf of the desired channel). As shown in Fig. 6A, the resistor is connected the position R3 as soon as the transmission ceases in the circuit, 10 15 20 25 30 35 40 to fig. 25 8204030-4 because the ÜÄTÃ ~ lead has a high level, while the lead from The integrator 18 is still low. Capacitor C2 discharged via the resistor, until the direct line from the voltage sensor gets low level. At this time generated a reset pulse and the device is reset to channel 0, phase 2, as shown in Fig. 6A, and also at the end of the signal CHO shown in Fig. 3J. As above is reduced the output signal from the voltage regulator shown in Fig. 3 relatively quickly, after the transmission has ceased. In this case the reset line gets a high level at the end of the door, when the direct line from the voltage sensor gets low level, while the recovery management again gets a high level at beginning of the next slot. If, on the other hand, the next gap starts before the time when the output signal from the voltage regulator has decreased to such a low value that the direct line from the voltage sensor level is high, the reset signal remains from gate G3 at high level between gaps. With respect to However, the mode of action makes no difference if the device is kept in channel 0, phase 2 between gaps or bi * _ this condition is brought to the beginning of each hatch. The most important is that the counter should be reset between ~ doors, if the device is still supplied with energy.

The signals in Fig. 6A relate to the reset in channel 0, phase 2, after the time constant for C2 / R3 has expired. The the second slot in this signal has similar period, but in this case, channel 11 is stimulated instead of channel 7. In all in other respects, the workflow is the same.

In the diagram of Fig. 6B, not only several channels can be stimulated within a single hatch but passes through all of the device fifteen channels under each hatch, even channels at the end after the last channel, which requires stimulation. Berry the wave was also transmitted, even when stimulation is not required.

If the device is initially assumed to be in channel 0, phase 2, the workflow is the same as described with regard to 6A, channel 7. But instead of closing the door at this point, channels 8-13 are traversed rapidly, after which the channel 14 is stimulated as required. Channel 15 then run fast. At the data interruption after the other 10 15 201 '25 30 ss- 40 8204030-4 26 'data pulse with a duration of 4 microseconds in it with channel 15 coordinated the pair was sent the carrier again. Someone re- position pulse is not generated because the direct line from the voltage sensor does not get low level. Instead'bring the counter from state 15 to state 0 and the clock Ü The pulse step is pulse-controlled in the usual way, so that channel 0, phase 1 (not phase 2) is represented.

The width of the pulse, which occurs while the device is in place itself in channel 0, phase 1, is arbitrary and this is indicated by p designation optional carrier. If the carrier appears, it gets direct line from the voltage sensor not low level. One short break before the next hatch, followed by a carrier break, controls the rocker stage FF1 to phase 2 according to Fig. 6B {At the end of this initial outbreak results in a data interruption, 'followed by a data pulse device to start operating in channel 1, phase 1. If the carrier was not sent continuously between hatches and If there is no long gap between the doors, the device will come on the other hand to_reset in the usual way, when the line from the voltage sensor gets low level. If the gap is so far, that all energy is lost, sets the carrier outbreak at beginning of the next slot device to channel 0, phase 2, such as described above in connection with the curves shown in Fig. 3, so that the first data pulse controls operation in channel 1, phase 1.

But if the gap is assumed to be so long that the direct the voltage from the voltage sensor may be low (a reset conditions), but not long enough to block energy supply to the logic elements, devices are placed in channel 0, phase 2. Since the reset line remains at a high level, as described above in connection with the curves in Fig. 3, set the original carrier output the break at the beginning of the next slot device to channel 0, phase 2, so that correct operation is ensured. . finally, the case where the logic is still energy is applied to the beginning of the next hatch, the device .en is in channel 0, phase 1 but the carrier was transmitted below longer than ¶MAX seconds between gaps. About the outcome of the time TMAX would be allowed to control reset to channel 0, phase 2 15 20 25 30 35 40 8204030-4. 27 and because the carrier interruption before the next slot typically does not has such a length that the direct line from the voltage the sensor may have a low level to reset the device to channel 0, phase 2 at the beginning of the next slot, would reset line at the beginning of the next door and the original carrier eruption would transfer devices to channel 1, phase 1 before the arrival of the first data pulse, so that synchronization would be lost. Of this cause the input signal É fi ï to the gate G6 prevents the time after TMAX, if the device is in duct _Q. Even if the TMAX time has elapsed, the device remains in the channel 0, phase 1 and is driven at the beginning of the next gap through phase 2, as required. It is thus clear that maximum flexibility is achieved, because the prosthesis works correctly independently of the length of carrier transmission between slots, Referring to Figs. 1 and 2, the manner in which on which the flip-flop FF1 is clock-controlled and on which the position of the rocker step from representing phase 2 to representing phase 1 controls the progress of the counter 20.

The calculator itself is conventional in that it includes takes four steps. The least significant step brings its output A to low level and its output Ä to high level, when it represents a 0, and the output A to a high level and output.Ã to low level, when it represents a 1. Same situation applies to the other three steps, whereby each step progresses, when the previous step is switched from one 1 to a 0. The four bit to sixteen bit decoder 22 are of the conventional type. Depending on_the conditions at the four two-conductor inputs, one of the sixteen low-level overhead lines. A connector for the decoder I is shown in Fig. 4, while its mode of action is quite clear for the person skilled in the art without any further description, in particular since such couplings can be purchased in the form of integrated circuits.

The method has also been described, in which the gates G1 and G2 " controls the output signals Üï and ÜÉ to a high level, when the device is in channel 0 (the ÖÉÜ line has a low level), and that way in which these gates are activated to work only, 10 20 25 -30 35 40 8204133043- 28 when the decoder 22 represents one of the channels 1-15. Which of the two gates, which bring their output to low level, depends on the state of the flip-flop FF1, whereby the output signal of the gate is low, as long as the corresponding data pulse is received.

The coupling part shown at the bottom in Fig. 2 is only symbolic. lisk. Sixteen output circuits are displayed for activating sixteen electrodes E1-E16. Successive pairs of these electrodes determine fifteen stimulation sites. Every sixteen electrodes must be connected, when the line CHO has a high level (channel 0) and it is for this reason that The connection is connected to each of the sixteen output circuits. na. Each pair of output circuits is connected to each of them the outputs T-TE on the decoder 22, so that a pair of output circuits can be activated, when each channel is operated. With the exception of the first and last output circuit is each output circuit connected to two of the decoder outputs, which all electrodes E2-E15 are affected by the stimuli of two different places. Only those with electrodes E1 and E16 coordinated output circuits are coordinated with each single place. The outputs ET and Éï are also connected to 'each of the output circuits, because it is the width of the pulse of each of these wires, as in fact controls the length of operation of a pair of output circuits. Initial the circuits of the pair being operated have relative polarities depending on the low level of the Üï and Éï lines, i.e. the phase of the two-phase pulse, which is generated.

Pig. 5A shows any (the Nth) of those with electro- the ones EN coordinated the intermediate output circuits, wherein this circuit has five inputs, the first of which represents channel 0, i.e. the line CHO in Fig. 2. This line has high level, each time channel 0 is selected. The embodiment shown in Fig. 5A the circuit is coordinated with channel N, so that they both with the inputs connected to this circuit from the decoder-22 are encoder outputs É and fi ïï. Referring to Fig. 2 it can be pointed out that each electrode ONE is selected for operation, when these outputs have a low level. The last two entrances are the ET and Éï lines, which are common to all 10 15 220 '25 30 40 29 8204030-4 electrode drive stage. The output stage of the circuit consists of a pair complementary field effect transistors 54, 56, as shown methods are connected across the power supply. From connecting the point between the two transistors is another line electrode EN.

When the device is operating in channel 0, the line ÉÉÜ is low level to bring the outputs from gates G1 and G2 to a high level. When the wires ÜT and Ü2 both have a high level in Fig. 5A, has the output signals from all gates 40, 42, 44 and 46 low level. Since both inputs to gate 50 has low level, its output signal has high level and has the output signal from inverter 52 low level. Consequently remains transistor 56 blocked. Although two of the entrances to the gate 48 also has a low level, the input signal at channel 0 on the CHO in Fig. 2 high level, so that the output signal from the gate 48 has a low level to keep transistor 54 conducting. Follow- actually the electrode EN is connected via the associated transistor 54 to the positive supply line together with other electrodes for the required operation in channel 0. ncm interconnection of all electrodes in the absence of need to stimulate a place, it is necessary to use the usual AC-switching output capacitors to reduce residual charge supply to a minimum and exclude electrode polarizing currents. When someone else channel is in operation, the input signal via channel 0 can be neglected, because it has a low level and does not affect the gate 48.

Between the two pulses in each pair or between the last the pulse in one pair and the first in the next has both wires ÉT and É2 high potential, because one the input of each of the gates G1 and G2 is connected with the data line, which has a low level, as soon as a data crime exists. Consequently, at least one of the the aisle of each of the gates 40, 42, 44 and 46 high potential, while the output signals from all gates are low In level. All inputs to gates 48 and 50 have thus lunda low level. As a result, the output signal from the gate 48 high level and the output of inverter 52 low level.

Both transistors 54 and 56 are kept off so that 10 15 20 25 30 35 40 8204030-4 3 ° the electrode EN floats. This is desirable during each data interruption, when the device is not operating in channel 0, and it is also the reason for connecting the resistor R3 1 fig. 1 1 the circuit at this time, since some other loading impedance is not present, which is connected across the con- the capacitor C2, which would enable its operation as reliable timer.

If the electrode BN is not one of the two electrodes, which was used for stimulation in a site whose channel is by the counter 20, both inputs N and N high potential in Fig. 5A. Although one of the the passages ÛT and ÜÉ can get low level, is one of the inputs 'N and N-1 connected to an entrance on each of the gates 40, 42, 44 and 46. When one entrance on each gate is held Dressed at a high level, the mode of action is the same as when the ÜT and ÉÉ hold one input signal to each gate at a high level. The two output transistors do not conduct * and the corresponding electrode is not affected by the stimulation. Now assume that place N is to be stimulated. During the first phase, the electrode EN should be connected to the negative side of the voltage source, when the line ÜT has a low level, and should during the second phase be connected to the voltage the positive side of the source, when the management Éï has a low level, for V to achieve, that a two-phase pulse is generated. When site N is stimulated, the input N has a low level. During phase 1, both have the input signals to gate 46 low level and its output high level. View the channel from gate 50 is consequently low, while the output the signal from the inverter 52 has a high level and the transistor 56 is kept leading. The entrance ÜÉ on gate 40 has a high level and the input Nïï at gate 42 has a high level, so that the the channels from both gates are low level. The output signal from gate 48 therefore has a high level and transistor 54 is held blocked. Only transistor 56 conducts and connects the electrode the ONE with the negative side of the feed source. During phase 2 i the same channel, both the input signal ÜT to the gate 46 ooh the signal ñïï to the grina 44 high level, so_to the signers from both gates have low level, while the output signal from gate 50 has a high level and the output of inverter 52 10 15 20 25 -30 35 40 31 8204050-4 low level, so that transistor 56 is kept off. While the signal from gate 42 is low level because its input Üï has a high level, the output signal from gate 40 now has a high level, because both its inputs Ü and Éï have a low level. The output signal from gate 48 therefore has a low level to control the transistor 54 to the conductive state, so that the electrode EN is connected to the positive side of the voltage source.

I When the previous channel N-1 is selected, the reverse operation must be performed take place. During phase 1, the electrode EN should be connected to The positive side of the DC voltage source and during phase 2 with the source negative side. When the input signal É has a high level, the output signal from gates 40 and 46 low level and can be neglected.

* During phase 1, the input signal Üï has a high level, while the output signal from gate 44 has a low level together with the output signal from gate 46 and the output of gate 50 have a high level and transistor 56 is kept non-conductive. But since both input signals the gate 42 has a low level, its output has a high level to control the transistor 54 to a conducting state. During phase 2, on the other hand, has the two inputs to gate 44 low level, while the output signal from gate 50 gets low level and transistor 56 conducts instead of transistor 54 to connect the electrode EN to the negative side of the supply source.

Fig. SB shows the output stage of the electrode E1, as only need to be selected under channel 1. During phase 1 of this channel should the electrode EN be connected to the negative of the supply source side and during phase 2 with its positive side. Under both the phases control the output circuit coordinated with the electrode E2 connections with opposite polarity. Below channel 0, the the signal to the gate 64 high level, so that its output signal has low level and keeps the transistor 66 conducting. Electrode E1 is connected via the transistor to the positive of the supply source side, to which all the other electrodes are connected at the same time. Because the input signal T has a high level below channel 0, the output signal from gate 62 is low level, so that transistor 68 remains blocked. When operating in someone channel other than channel 1 has the channel input signal high level. Out- the signal from gate 62 is low level and holds the transistor 68 thus non-conductive, while the output signal from gate 60 has low 10 15 20 25 30 35 40 8204030-4 32 level together with the input signal for channel 0 and the output signal from the gate 64 has a high level and holds the transistor 66 blocked. Between pulses, both wires have Ü? and Ü2 high potential, so that the output signals from gates 60 and 62 have low. When the two inputs to gate 64 are low level, its output signal is high level and keeps the transistor 66 blocked. When the output of gate 62 is low, it is held the transistor 68 is blocked and the electrode E1 floats as required.

But if channel 1 is selected, the input signal T has a low level, while in ~ the signal ET has a low level during phase 1. When both input signals to the gate 62 has a low level, its output signal has a high level and controls the transistor 60 to a conducting state. Since the channel É2 has a high level, the output signal from gate 60 is low level, so that transistor 66 remains blocked. During phase 2 i channel 1, on the other hand, has the output signal from gate 60 high level, while the output signal from gate 62 is low level, so that transistor 66 conducts instead of transistor 68.

Fig. 5C shows the output stage coordinated with the electrode E16.

Below channel 0, the input signal to gate 74 has a high level, so that its output signal is low level and keeps the transistor 76 leading. Since the input signal 16 has a high level, the output signal has from gate 72 low level and keeps transistor 78 locked.

Between data pulses, both the line Üï and the line É2 have high level, so that the output signals from gates 70 and 72 have low level and keeps both output transistors blocked.

During each active channel except channel 15, the input signal TÉ is high level, so that the output signals from gates 70 and 72 are low level. The low level output signal from gate 72 holes1 transistor 78 is blocked and has the high level output of gate 74 and keeps transistor 76 non-conductive, since both of the gates input signals are low level.

But below channel 15, the input signal 16 has a low level and has an effect not on gates 70 and 72. During phase 1 in channel 15, the ÜT signal is low, while the output signal of the gate 70 is high level and keeps transistor 76 conductive when both of its signals have low level. Since the input signal É2 has a high level, 10 15 20 25 30 33 s2o4o3oÄ4 the output signal from gate 72 is low level and keeps the tower 78 blocked. This is required because the sixteenth starting the circuit selected only under channel 15 must connect electrode E16 with the positive side of the supply source during phase During phase 2 in channel 15, both input signals to the grating the 72 low level, while its output signal has a high level. Transis- tower 78 is now conductive and connects the electrode E16 to the supply negative side of the source. Because the input signal ÜT is high level, the output signal from gate 70 is low level and holds transistor 76 is non-conductive.

According to the prior art, the pulse amplitude has changed as well as the pulse width for stimulation of auditory nerves. The intensity of a response to electrical stimulation is related to it the charge emitted, whereby the amount of charge can be controlled according to nom either or both of current amplitude and pulse width. Also if the response is not exactly proportional to the integral of the pulse, some have considered that, while changing either the pulse amplitude tud or pulse width is an effective aid for control of perceived intensity, the two techniques are not equivalent and that the results of the same are of a different nature. One explanation for this phenomenon is that during a very short pulse all nerve endings, the thresholds of which are exceeded, come to be triggered synchronously, while during a longer pulse with lower amplitude different groups of nerve endings will be triggered, when their different thresholds are exceeded at different times during supply of the pulse. Because the decoding hearing mechanism in the ascending ear canal and cerebral cortex have the ability to temporarily distinguish very fine, can a deviant sound perceived. While the illustrated embodiment of the invention is intended for changing the pulse width only, one thus has discovered that it can also be beneficial to use one in the form of pulse amplitude equipment simultaneously or even alone to control heart rate intensity.

Claims (1)

10 15 20 25 30 35 8264030-4 34 Patent claims 1. Implantable. tissue-stimulating prosthesis, especially for cochlea. comprising a number of electrodes (El - E16). which are paired in pairs with their respective stimulation sites (1-15) and with at least most of the electrodes. which is part of each of at least two different pairs. and a detector (Ll. Cl) for detecting a transmitted information signal. which is characteristic of the stimulation intensity. required for the stimulation sites (1 - 15). and on the other hand, a detector controlled by the detector (12) for supplying energy to the electrode pairs depending on the activity of the detector, characterized in that the energy supply device (12) supplies energy to only a single pair of electrodes at any one time and operates so fast. that at least two electrode pairs are deliverable energy one after the other within a period of time. which enables. that the various stimuli of places (l - 15) are perceived as simultaneously occurring. A prosthesis according to claim 1, wherein the time period (TMAX) is less than one millisecond, 3. A prosthesis according to claim 1 or 2, characterized in that the information signal is characteristic of the stimulation intensity in the form of pulse width. Prosthesis according to claim 3, characterized in that the information signal is formed within successive time slots. each of which comprises a number of pulses in a predetermined sequence. corresponding to the different stimulation sites (1 - 15). and that the energy supply device (12) is capable of supplying energy to subsequent electrode pairs in a predetermined sequence. corresponding to the predetermined pulse sequence within each slot. Prosthesis according to one of Claims 1 to 4, characterized in that a device ([0]. Figs. 5A - SC) for interconnection is provided. 4 35 or short circuit of all electrodes. a device (CA. ST2) for detecting a pulse width in the information signal. exceeding a predetermined width. and a device (G6. G3. 20). which reacts to the operation of the detection device and affects the short-circuit device. Prosthesis according to claim 4, characterized in that a stimulation site (1 - 15) within an information signal slot is represented by a corresponding pair of pulses and that the energy supply device (12) supplies a pair of successive current pulses with opposite polarity to each electrode- par. which is supplied with energy. and controls the intensity of each of these current pulses depending on the width of another of the different pairs of information signal pulses. of entering Prosthesis according to claim 1, characterized in that the formation signal is formed within successive ~ eM time slots. which individually comprise a number of information elements in a predetermined order. corresponding to different stimulation sites. and that the energy supply device (12) is capable of supplying energy to successive electrode pairs in a predetermined sequence, corresponding to the predetermined information element sequence within each slot. A prosthesis according to claim 7, characterized in that the energy supply device for supplying energy to the electrode pair. which is coordinated with a stimulation point represented within a gap. first pass by and for energy supply select all electrode pairs. which is earlier in the predetermined sequence. and that each such previously selected electrode pair. which is coordinated with any stimulation site. which has no requirement for perceptible stimulation. no energy is supplied from the device in the form of perceptible current pulses- SBI. know that successive electrode pairs in the predetermined sequence have one electrode in common. 10 15 20 25 30 35 Prosthesis according to claim 14. 8204030-4 36 10. A prosthesis according to claim 1, characterized in that a stimulation site in the information signal is represented by a corresponding pair of pulses. ll. A prosthesis according to any one of claims 1 to 10, characterized in that the energy supply device (12) comprises means (or 62) for switching the polarity of a single energy source across each electrode pair to obtain current pulses of opposite polarity. A prosthesis according to claim 1, characterized by means (10) for forming an energy source for the detector and the energy supply device on the basis of the detected information signal. l3. A prosthesis according to claim 12, characterized by a y device (16) for detecting a predetermined decrease in the level of the energy source. A prosthesis according to claim 1, characterized by means ([p]. Fig. 5A-SC) for inhibiting energy supply to all electrodes. bodies (G6. G3) to determine. if the detected information signal is incompatible with a predetermined shape. and a device (20) which responds to the activity of the determining means and affects the inhibiting means. know that inhibition means also have the task of short-circuiting all electrodes. A prosthesis according to claim 14 or 15, characterized by a device (CHO) for synchronizing the operation of the energy supply device with the information signal and a device (27). which responds to the activities of the determining bodies and controls the operation of the synchronizing device.