SE392982B - Cirkulerande minne - Google Patents

Cirkulerande minne

Info

Publication number
SE392982B
SE392982B SE7302148A SE7302148A SE392982B SE 392982 B SE392982 B SE 392982B SE 7302148 A SE7302148 A SE 7302148A SE 7302148 A SE7302148 A SE 7302148A SE 392982 B SE392982 B SE 392982B
Authority
SE
Sweden
Prior art keywords
circularing
memory
circularing memory
Prior art date
Application number
SE7302148A
Other languages
English (en)
Swedish (sv)
Inventor
E Cicognani
A Caldarella R Lamartina
Original Assignee
Sits Soc It Telecom Siemens
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sits Soc It Telecom Siemens filed Critical Sits Soc It Telecom Siemens
Publication of SE392982B publication Critical patent/SE392982B/xx

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G06F5/085—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register in which the data is recirculated
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C21/00—Digital stores in which the information circulates continuously
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
SE7302148A 1972-02-16 1973-02-15 Cirkulerande minne SE392982B (sv)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT20619/72A IT959546B (it) 1972-02-16 1972-02-16 Memoria a ricircolazione

Publications (1)

Publication Number Publication Date
SE392982B true SE392982B (sv) 1977-04-25

Family

ID=11169636

Family Applications (1)

Application Number Title Priority Date Filing Date
SE7302148A SE392982B (sv) 1972-02-16 1973-02-15 Cirkulerande minne

Country Status (2)

Country Link
IT (1) IT959546B (it)
SE (1) SE392982B (it)

Also Published As

Publication number Publication date
IT959546B (it) 1973-11-10

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