SE349424B - - Google Patents
Info
- Publication number
- SE349424B SE349424B SE00034/70A SE3470A SE349424B SE 349424 B SE349424 B SE 349424B SE 00034/70 A SE00034/70 A SE 00034/70A SE 3470 A SE3470 A SE 3470A SE 349424 B SE349424 B SE 349424B
- Authority
- SE
- Sweden
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US78882269A | 1969-01-03 | 1969-01-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SE349424B true SE349424B (xx) | 1972-09-25 |
Family
ID=25145670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SE00034/70A SE349424B (xx) | 1969-01-03 | 1970-01-02 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US3559003A (xx) |
| JP (1) | JPS4826667B1 (xx) |
| CH (1) | CH499204A (xx) |
| DE (1) | DE1965565A1 (xx) |
| FR (1) | FR2027700B1 (xx) |
| GB (1) | GB1269130A (xx) |
| NL (1) | NL7000034A (xx) |
| SE (1) | SE349424B (xx) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3667008A (en) * | 1970-10-29 | 1972-05-30 | Rca Corp | Semiconductor device employing two-metal contact and polycrystalline isolation means |
| DE2109814C3 (de) * | 1971-03-02 | 1974-06-27 | Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt | Halbleiteranordnung |
| FR2140309B1 (xx) * | 1971-06-09 | 1975-01-17 | Sescosem | |
| US3737742A (en) * | 1971-09-30 | 1973-06-05 | Trw Inc | Monolithic bi-polar semiconductor device employing cermet for both schottky barrier and ohmic contact |
| DE2554626C3 (de) * | 1975-12-04 | 1981-05-07 | Siemens AG, 1000 Berlin und 8000 München | Abschirmeinrichtung und Verfahren zu deren Aufbringung |
| JPS57100755A (en) * | 1980-12-15 | 1982-06-23 | Fujitsu Ltd | Semiconductor device |
| US6737326B2 (en) * | 2000-06-01 | 2004-05-18 | Texas Instruments Incorporated | Method of integrating a thin film resistor in a multi-level metal tungsten-plug interconnect |
-
1969
- 1969-01-03 US US788822A patent/US3559003A/en not_active Expired - Lifetime
- 1969-11-17 GB GB56104/69A patent/GB1269130A/en not_active Expired
- 1969-11-21 CH CH1736069A patent/CH499204A/de not_active IP Right Cessation
- 1969-12-04 FR FR6941857A patent/FR2027700B1/fr not_active Expired
- 1969-12-08 JP JP44097926A patent/JPS4826667B1/ja active Pending
- 1969-12-30 DE DE19691965565 patent/DE1965565A1/de not_active Withdrawn
-
1970
- 1970-01-02 NL NL7000034A patent/NL7000034A/xx not_active Application Discontinuation
- 1970-01-02 SE SE00034/70A patent/SE349424B/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| FR2027700A1 (xx) | 1970-10-02 |
| GB1269130A (en) | 1972-04-06 |
| NL7000034A (xx) | 1970-07-07 |
| FR2027700B1 (xx) | 1973-10-19 |
| CH499204A (de) | 1970-11-15 |
| US3559003A (en) | 1971-01-26 |
| DE1965565A1 (de) | 1970-07-16 |
| JPS4826667B1 (xx) | 1973-08-14 |