SE301065B - - Google Patents
Info
- Publication number
- SE301065B SE301065B SE5709/66A SE570966A SE301065B SE 301065 B SE301065 B SE 301065B SE 5709/66 A SE5709/66 A SE 5709/66A SE 570966 A SE570966 A SE 570966A SE 301065 B SE301065 B SE 301065B
- Authority
- SE
- Sweden
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US45191665A | 1965-04-29 | 1965-04-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| SE301065B true SE301065B (he) | 1968-05-20 |
Family
ID=23794238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| SE5709/66A SE301065B (he) | 1965-04-29 | 1966-04-27 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US3420991A (he) |
| DE (1) | DE1499840B2 (he) |
| GB (1) | GB1093518A (he) |
| SE (1) | SE301065B (he) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3500318A (en) * | 1967-11-02 | 1970-03-10 | Sperry Rand Corp | Plural communication channel test circuit |
| JPS4912499B1 (he) * | 1969-07-16 | 1974-03-25 | ||
| US3727039A (en) * | 1971-08-02 | 1973-04-10 | Ibm | Single select line storage system address check |
| JPS6027120B2 (ja) * | 1977-11-04 | 1985-06-27 | 日本電気株式会社 | プログラマブルメモリ |
| JPS5693189A (en) * | 1979-12-18 | 1981-07-28 | Fujitsu Ltd | Field programable element |
| DE3232215A1 (de) * | 1982-08-30 | 1984-03-01 | Siemens AG, 1000 Berlin und 8000 München | Monolithisch integrierte digitale halbleiterschaltung |
| CA1203631A (en) * | 1982-11-26 | 1986-04-22 | John L. Judge | Detecting improper operation of a digital data processing apparatus |
| US4608669A (en) * | 1984-05-18 | 1986-08-26 | International Business Machines Corporation | Self contained array timing |
| US4686456A (en) * | 1985-06-18 | 1987-08-11 | Kabushiki Kaisha Toshiba | Memory test circuit |
| US5107501A (en) * | 1990-04-02 | 1992-04-21 | At&T Bell Laboratories | Built-in self-test technique for content-addressable memories |
| JP3204450B2 (ja) | 1998-04-15 | 2001-09-04 | 日本電気株式会社 | アドレスデコード回路及びアドレスデコード方法 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2958072A (en) * | 1958-02-11 | 1960-10-25 | Ibm | Decoder matrix checking circuit |
| NL285817A (he) * | 1961-11-22 |
-
1965
- 1965-04-29 US US451916A patent/US3420991A/en not_active Expired - Lifetime
-
1966
- 1966-04-15 GB GB16619/66A patent/GB1093518A/en not_active Expired
- 1966-04-22 DE DE19661499840 patent/DE1499840B2/de active Pending
- 1966-04-27 SE SE5709/66A patent/SE301065B/xx unknown
Also Published As
| Publication number | Publication date |
|---|---|
| US3420991A (en) | 1969-01-07 |
| GB1093518A (en) | 1967-12-06 |
| DE1499840B2 (de) | 1970-09-24 |
| DE1499840A1 (he) | 1970-09-24 |