SE1330066A1 - Process for manufacturing vertical elongated nanostructures and nanostructures thereof - Google Patents

Abstract

A method (1000) for manufacturing a plurality of elongate vertical nanostructures (100, 200, 300, 400, 500, 600, 800a, 800b, 900) on the same substrate (101, 201, 301,401, 501, 601) which involve. (1001) providing at least one hole (102, 202, 302, 402, 502, 602, 802a, 802b, 902) in contact with a substrate (101, 201, 301, 401, 501, 601), (1002) to incorporate nanoparticles (103, 203, 303, 403, 503, 603, 803a, 8003b) in at least one of said holes (102, 202, 302, 402, 502, 602, 802a, 802b) from a nanoparticle suspension having an evaporating liquid front (105), and (1003) heating the nanoparticles (103, 203, 303, 403, 503, 603, 803a, 803b, 903) in contact with that substrate, preferably above the melting point of the nanoparticles. With the method it is possible to grow a plurality of nanowires with different material combinations on the same substrate, preferably silicon substrate.

Description

Particle-assisted nanowire growth is a general method of growth nanowires where the most well-known technology is to use gold particles which are aerosol particles. Gold particles are deposited on the substrate randomly and with a large spread on the size of the gold particles.

When the plant temperature is reached, a gas flow of III is switched on feedstock to the MOVPE reactor. The basic substances are incorporated in the gold particles by diffusion and at a specific concentration become the gold particles are supersaturated, leading to nanowire growth i.e. nucleation of semiconductor materials. The nanowire growth can be stopped by turn off the V gas flow. The growth rate depends partly on the supersaturation, the concentration of reactants and the temperature. Particle assisted nanowire growth can be described with the VLS model and the VSS model.

The document “Challenges for Nanoscale MOSFETs and Emerging Nanoelectronics "describes the problems with nanoelectronics. The document describes how variations in nanowire dimensions can cause perturbations the charge carrier potential and dispersion that can degrade transport the characteristics. Another problem is that variations in nanowire diameter leads to variations in threshold voltage. To reduce the morphological the variance for nanowire-field-effect transistors is therefore one of the most difficult the problems to solve for a functioning transistor technology. The article describes also the problem of designing new contacts for the components. In order to be able to contact the nanowires, the contacts must be able to be made smaller than 10 nm in diameter. When the diameters of metal electrodes are scaled down to the mean free path of the electrons leads to the scattering of electrons at the grain boundaries of the metals.

Document US20100176459A1 describes a transistor component with two vertically grown nanowires with wrap-around connectors, i which one of the nanowires' threshold voltages differs from the other transistor. The problem with the technology is to grow two different nanowires in it the same process where the nanowires can be doped differently for a p-channel and an n- channel. Another problem with the technology is to use different material system for a p-channel and an n-channel.

US8330143B2 describes a field effect transistor with a wrap gate plug. The problem with the field effect transistor is contacting the nanowires with the respective three terminals: emitter, collector and gate terminals. In particular, there are difficulties in contacting the nanowires bottom of the substrate with vertical contacts due to the difficulty of sputter evaporated metal in deep nano holes. Another problem with technology is that vaporized metals used to make the contacts have random grain boundaries in the range 5 to 500 nm, giving rise to scattering of electrons for nanowire CMOS, which prevents ballistic transport through the contacts.

The problem of growing nanowires in a controlled way with MOCVD whereby using nanoparticles has been unresolved since the 90s at that time discovery by Lieber et al. at Harvard, Yang et al. at Berkeley and Samuelson et al. at Lund University. Today it is still used the aerosol method in research where the deposition of nanoparticles on the substrate causes some nanowires to grow larger than others. This makes that the technology in practice becomes uncontrollable for silicon nanowire-based CMOS (Silicon nanowire CMOS) at nodes 14 nm, 10 nm and 5 nm, but also III-V based CMOS. Furthermore, the mechanism for growing microwires is a disordered manner of gold particles according to the VLS mechanism known since 70- the number.

The article “Direct assembly of nanoparticles for large-scale fabrication of nanodevices and structures "J Nanopart Res (2008) 10: 947-954" shows one ways to incorporate gold nanoparticles into furrows using one electric field s.k. "electric field direct template-assisted assembly".

The document also shows how gold nanoparticles can be incorporated between two lithographically defined metal contacts. The problem with technology is that it is very difficult to use for nanowire growth as it requires an electric field, which also limits the use considerably to mainly metal particles.

The document “Ways towards the scaleable integration of carbon nanotubes into silicon based technology, Diamond and Related Materials 13 (2004) 354-361 ", shows how carbon nanotubes grow from a catalyst particle in a nanohole.

One problem with the technology is that the method is dependent on fragmentation catalytic material, which causes particle islands to grow according to Volmer-Weber heating mechanism. This in turn leads to misgrowth with divorced sizes of carbon nanotubes. Another problem with technology is control plant of single-walled carbon nanotubes with monodisperse sizes for one CMOS technology.

The article "Silicon nanowires: The Next Big ThingW 'in chip design, http://www.theregister.co.uk/2012/03/16/silicon_nanowires "describes how silicon nanowires will be the next step in the development of CMOS and the document “Catalyst preparation for CMOS compatible silicon nanowire synthesis, Nat Nanotechnol. 2009 Oct; 4 (10): 654-7 "describes the problem with silicon nanowire-based CMOS. Metallic contamination was the key to the discovery of semiconductor nanowires, but today this is what stands in the way of using these in the semiconductor industry. This is because that the metal particles used for nanowire growth are not compatible with standard CMOS process technology. Nanowire synthesis with the metals which are CMOS compatible are aluminum and copper, but these require temperatures above 450 ° C which is the maximum temperature that is allowed for CMOS processes. The document describes that copper oxide for particle-assisted nanowire plant.

Article “Continuous gas-phase synthesis of nanowires with tunable properties. Nature 2012 Dec 6; 492 (7427): 90-4 "describes the new the direction of epitaxial growth of nanowires with so-called aerotaxi. The technique is based on the nanowires growing already in the gas phase on metal particles.

The problem with the technology is that the nanoparticles are manufactured by so-called DMA, which means that the control over the nanoparticle size is limited and has large dispersion for the size of the nanoparticles.

Article "InP Nanowire Array Solar Cells Achieving 13.8% Efficiency by Exceeding the Ray Optics Limit, 18 January 2013: 263 ”describes one method to use nanoimprint lithography with large gold plates that are 180 nm in diameter to achieve efficiencies of 13.8% for nanowire-based p-i-n solar cells. The problem with technology is that when growing of smaller nanowires do not nucleat the lithographically defined ones the gold plates as gold plates of a larger size on the nanoscale grow on cost of smaller gold plates on the nanoscale by so-called Ostwald- ripening. The problem is not limited to III-V semiconductors, but also nitride plant e.g. GaN nanowires using a lithographic mask.

The problem gets worse for smaller size of nanowires. This leads to problems in achieving ballistic transport of charge carriers.

To deposit nanocolloids on a substrate e.g. with s.k. spin-coating for nanowire growth is a method that has not been successful. The problem with the technique is that the nanocolloids are deposited randomly on the substrate, leading to unfermented nanowire growth.

Articles “Journal of Light-Emitting Diodes Vol 2, No. 1, 2010 ”describes the problem of especially green III-N-based LEDs. Although high-efficiency LEDs based on GaN are available on the market, so is the performance of InXGabXN-based LEDs with green electroluminescence still poor. This is because the high indium the content required in the active layer for green emission causes problems.

In particular, it is the high temperature during growth of pGaN that causes that indium migrates out of the active layer. This causes poorer performance too these LEDs. Furthermore, the multiple quantum wells are special difficult to configure due to Stark effects ie the polarization field for polar GaN. When growing heterostructures on non-polar planes for nanowires the heterostructures cause voltage, which gives rise to Stark effects in the same way as when growing on polar planes when growing in bulk. This leads to an unfavorable blue shift of the electroluminescence.

The book “Oxide and Nitride Semiconductors: Processing, Properties and Applications ”describes how the growth rate and that a high reactor pressure is crucial for pGaN with a high hole concentration where pGaN grows by one CpzMg / NHg ratio of 1.5 - 10-3 and a growth rate of 3 μm / h. To growing the nanowires at a high reactor pressure is not possible with self-catalytic pGaN core strands.

Another method is to use a self-organized layer of nanocolloids on a substrate. The problem with technology is that it becomes far too close between the particles when the distance between the nanowires in the practice becomes negligible and leads to malnutrition.

Furthermore, those skilled in the art consider the technology to use colloidal particles to nanowire plant has too low purity. This is stated in the licentiate dissertation Maria Messing, Gold Particles for Growth of Semiconductor Nanowires, 2009 ”. Colloidal nanoparticles are the least pure compared to the aerosol method and nanoimprint lithographically defined particles, which would be an obstacle to using these for nanowire growth.

Document "G.-C. Yi (ed.), Semiconductor Nanostructures for Optoelectronic Devices, NanoScience and Technology, Springer-Verlag Berlin Heidelberg, 2012 ”describes the general technical position for VLS-assisted nanowire growth for optoelectronics. The document describes how certain problems must be solved to use the nanowires for optoelectronics. One problem is control over diameter, vertical growth, core shell nanowires and composition control including doping of the nanowires. Another problem is to grow nanowires with gold nanoparticles for silicon nanowire CMOS. The gold particles contaminate the silicon nanowires as a result of alloying with silicon.

The contamination can cause a degradation of the optical properties for the nanowires through the interference doping in the band gap. Further is not gold particles compatible with CMOS due to the high diffusivity, which causes gold to migrate to the surface and make it difficult to control the plant of silicon nanowires. The document describes platinum and aluminum as suitable candidates for silicon nanorabase civiosis.

The document “High-Performance Nanowire Electronics and Photonics and Nanoscale Patterning on Flexible Plastic Substrates, McALPINE et al .: HIGH-PERFORMANCE NANOWIRE ELECTRONICS AND PHOTONICS AND NANOSCALE PATFERNING ”describes the general technical position for nanowire growth on flexible plastic substrates. Plastic substrate can nanomemplated by nanoimprint lithography at room temperature.

The optical properties of nanowires depend on their diameter.

The band gap for silicon nanowires becomes larger when the diameters of the silicon nanowires is less than 10 nm. Diameters of silicon nanowires smaller than 10 nm changes the bandgap from indirect to direct for silicon. Less nanoparticle radius increases the chemical potential, which makes it difficult to grow small diameter nanowires to achieve 1D effects with radial restriction of charge carriers. By controlling the bandgapets size at the nanoscale with the nanoparticles can the luminescence from the nanowires are controlled.

Furthermore, the document describes the compatibility between metal particles for plant with VLS mechanism must be explored. The problem with technology is that although nanowires can be grown with simplicity from nanoparticles must these be compatible with CMOS. Another problem is that upscaling of nanowire technology for standardized nanowire growth and reliable nanowire growth processes.

Document US 20110315553A1 describes an inexpensive way to clean colloidal nanoparticles in as little as 2 minutes with an electric cleaner.

The nanoparticles are cleaned of unwanted material.

In the following, the problems of the prior art will be described summarized: A problem with the prior art is that the positions of the nanoparticles become random.

Another problem is that it is difficult to use the aerosol method as causes great variance in the aerosol particles.

Another problem is that it is difficult to do more advanced components with vertical nanowires as they grow by different lengths, which where the growth rate depends on the radius of the nanoparticle.

Another problem is that nanowires with nanocolloids directly on one substrate gives random deposition.

Another problem is to contact vertically grown nanowires, in order to manufacture electrical components, is difficult or impossible with the known the technique.

Another problem is that the dispersity of the hole sizes with nanoimprint lithography, which is the most commercial lithographic method to pattern substrates with for nanowire growth, causes misgrowth then the dispersity affects the nucleation barrier and the diameters of the nanowires determined by the dispersed hole sizes.

Another problem is to achieve high p-doping for pn-diodes based on III-N nanowires. Although the quantum well provides high intensity for photoluminescence and has the correct wavelength in the photoluminescence spectrum must the doping of the nanowires gives rise to a band diagram for a diode structure when the nanowire is used as a diode. There is a need to provide options for growing III-N nanowires.

Problem solving The present invention seeks to eliminate, prevent or overcome them mentioned problems with the prior art, which would constitute a step against the application of nanowires with controllable nanowire growth through that it has the features specified in the following claims. The also solves the problem of growing nanowires of different material systems on the same substrate, but also different doped nanowires. It also solves the problem of contacting vertically grown nanowires. This would in addition, constitute an important step towards applications of nanowires for next generation integrated circuits (ULSI) for chip nodes 14 nm, 10 nm and 5 nm. The present invention also solves the problem of manufacture nanowire-based monitors through R (III-V), G (III-V), B (III-N) - nanowire LEDs. The present invention also solves the problem of increase the efficiency of nanowire-based solar cells by a number of pn- transitions.

BRIEF DESCRIPTION OF THE INVENTION What is meant by this document by an all-around gate electrode or an all-around electrode is an electrode that substantially encloses an elongate nanostructure such that the electrode is in contact with an oxide layer which encloses said elongate nanostructure in which said the oxide layer is in contact with said elongate nanostructure to form a MOS (Metal Oxide Semiconductor) structure.

A first aspect of the invention relates to a method (1000) of manufacturing a plurality of elongate vertical nanostructures (100, 200, 300, 400, 500, 600, 800a, 800b, 900) on the same substrate (101, 201, 301,401, 501, 601) including; (1001) to provide at least one hole (102, 202, 302, 402, 502, 602, 802a, 802b, 902) in contact with a substrate (101, 201, 301, 401, 501, 601), (1002) to incorporate nanoparticles (103, 203, 303, 403, 503, 603, 803a, 8003b) in at least one of the mentioned holes (102, 202, 302, 402, 502, 602, 802a, 802b) from a nanoparticle suspension which includes an evaporating liquid front (105), and (1003) for heating the said nanoparticles (103, 203, 303, 403, 503, 603, 803a, 803b, 903) in contact with said substrate, preferably over that of the nanoparticles melting point.

A second aspect of the invention relates to a nanowire component member (4000, 4100, 8000, 9000) including; a first plurality of nanowires (300, 400) and a second plurality of nanowires (400, 800a, 800b, 900) in which it said first plurality of nanowires (300, 800a, 800b, 900) comprise at least one pn junction and the said second plurality of nanowires comprises at least one pn junction, in which said first plurality nanowires and the said second plurality of nanowires are different, in which it said first plurality of nanowires and said second plurality nanowires are grown on the same substrate.

A third aspect of the invention relates to a CMOS nanostructure system (6000) including; a first MOS nanostructure and a second MOS nanostructure, a first all-around gate electrode (5001a) and a second all-around gate around-gate electrode (5001b), in which the first MOS nanostructure includes; an n-doped portion of a substrate (501a), an electrical elongate terminal electrode (500a, 500a, 600a, 600b) perpendicular to the said the substrate and a vertically grown p-doped nanowire (400a), and in which said n-doped substrate (501a) is in contact with it said p-doped nanowire (400a) and in contact with said elongated terminal electrode (500a, 600a), and a second MOS nanostructure, in which the second MOS nanostructure comprises a p- doped part of a substrate (501b), an electrically elongated terminal electrode (500b, 600b) perpendicular to said substrate and a vertical plant n-doped nanowire (400b), and in which said n-doped portion of the substrate (501a) is in contact with said p-doped nanowire (400a) and in contact with said elongate terminal electrode (500a, 600a), and in which said p-doped portion of the substrate (501b) is in in contact with said n-doped nanowire (400b) and in contact with said elongate terminal electrode (500b, 600b), and in which the first p-doped nanowire (400a) and the second n-doped the nanowire (400b) is in electrical contact (5002), in which the said the first all-around gate electrode (5001a) is in electrical contact with it said first β-doped nanowire (400a) and said second universal the around-gate electrode (5001b) is in electrical contact with the said other n-doped nanowires (400b).

An advantage of the invention is that the so-called Ostwaldmognaden (Ostwald ripening) for nanowire synthesis decreases, allowing control over nanowire growth increases with continued decrease in the size of nanowires and the nanowire diameter of the transistor nodes 14 nm, 10 nm and 5 nm.

Another advantage of the invention is that it becomes possible to use different ones material system for a p-channel and an n-channel e.g. p-doped InSb for a p- channel with high hole mobility and an nInAs with high n-doping for n- the channel.

Another advantage of the invention is to grow nanowires according to the invention is that the process uses synthetically produced nanoparticles from reagents so that it is possible to grow nanowires with non-metals on in an orderly and simple manner, compared to evaporation methods.

Another advantage of the invention is to grow nanowires according to the invention is that orderly nanowire growth becomes independent of the monodispersity for hole size for nanoimprint lithography to make holes down to the substrate through a mask.

Another advantage of the invention is to grow nanowires according to the invention is that the process leads to significantly higher control over the nanowire plant when the diameter of the nanowires decreases, by controlling the size of the colloid particles in the synthesis of the colloid particles and their incorporation on a substrate.

Another advantage of the invention is that one does not need to use it a phosphorescent layer which for e.g. blue LEDs to get white light then a plurality of nanowires with different luminescence wavelengths can be grown on the same substrate in separate processes.

Another advantage of the invention is that it becomes possible to grow differently doped nanowires with nanoparticles on the same substrate.

Another advantage of the invention is that it becomes possible to grow III-V- nanowires and III-N nanowires on the same substrate.

Another advantage of the invention is that it becomes possible to contact vertically grow nanowires.

Another advantage of the invention is that it is possible to grow different nanowires with different nanoparticles.

Another advantage of the invention is that it is possible to grow nanowires with oxide particles or non-metals.

Another advantage of the invention is that it is possible to grow a plurality nanowires with different material combinations on the same substrate, preferably silicon substrate.

Another advantage of the invention is that the positions of the nanoparticles become predictable for contact with electrical contacts.

Another advantage of the invention is that it becomes easier to do more CMOS components with vertical nanowires as they grow with the same lengths, where the growth rate depends on the radius of the nanoparticle.

Another advantage of the invention is that the nanowire dimensions become O. . .. O O 0 independent of the dispersion of the nanohalo for nanohal, then the nanotradar ... . ... . O lengths, diameters, and nucleation are determined by the nanoparticles | halen.

Another advantage of the invention is that the nanoparticles make it so possible to grow pGaN-III-N core wires with side walls as A-plane. For nucleation of pGaN core wires with gold particles is achieved a much higher growth rate, which increases the p-doping of core threads.

Another advantage is that the nucleation of III-N core wires becomes easier to check with nanoparticles with monodisperse radius.

Another advantage is that it becomes possible to grow III-N nanowires in a first process at high temperature, and then grow two pieces differently sets of III-v nanowires for R (111-v) G (111-v) BuH-m energy efficient monitors with high brightness per watt.

Another advantage of growing the III-N nanowires on buffer layers is that dislocations in the buffer layer do not nucleat to the nanowires.

Another advantage of the method of growing the nanowires as silicon substrate / pGaN / InXGabXN / nGaN is that contacts to bulk-c-plane-pGaN can be made.

Another advantage of the invention is that it becomes possible to contact nanowires with metallic carbon nanotubes grown from gold particles for both silicon nanowire CMOS and III-V CMOS with high-dielectric materials e.g. hafnium oxide HfO2_ Another advantage is that the nanowires can be contacted with metal lis carbon nanotubes smaller than 10 nm in diameter. This leads to when the electrodes are scaled down to the mean free path of the electrons, none occurs scattering of electrons at the grain boundaries as for the metals.

Another advantage is that metallic carbon nanotubes can be grown single-walled with controlled lengths and diameters.

Another advantage is that variations in nanowire dimensions decrease, which reduces perturbations for charge carrier potential and scattering as can degrade the transport characteristics of CMOS transistors.

Another advantage is that the reduced variation in nanowire diameter leads to reduced variations in threshold voltage for nanowire field effect transistors.

Another advantage is that it becomes possible to functionalize single-walled carbon nanotubes for bionanosensors.

Another advantage is that it will be possible to grow a number of nanowires with different multiple p-i-n transitions on the same substrate, which increases efficiency of nanowire-based solar cells.

DESIGN OF FIGURES In the following, the invention will be described in more detail with reference to the accompanying figures, where: Fig. 1A is a process diagram of the method 1000 to be incorporated nanoparticles in nanoholes.

Fig. 1B-Fig. 1D schematically describe the method in which a wafer is immersed down into a nanoparticle suspension during evaporation of solvent.

Fig. 2 is a schematic figure of III-V nanowires or silicon nanowires with nanoparticles at the top of the nanowires and describes one etchable bar structure covering a nano hole.

Fig. 3A schematically describes a cross section of a hexagonal III-N- nanowire with M-plane facets grown with a nanoparticle seen from the side on buffer layer with holes down to the buffer layer through a mask.

Fig. 3B is a schematic top view of a hexagonal III-N nanowire with vertical M-plane facets grown with a nanoparticle. The nanowire has a p- doped core wire, an intrinsic shell layer on the p-doped core wire and a outer n-doped shell layer.

Fig. 3C is a schematic top view of a triangular III-N nanowire grown with a nanoparticle. The nanowire has a p-doped core wire, an intrinsic shell layer on the p-doped core wire and an outer n-doped shell layer.

Fig. 3D is a schematic top view of a triangular III-N nanowire with LED structure grown with a nanoparticle. The nanowire has the LED structure pGaN core wire / pAlGaN shell / iGaN shell / InHGaXN shell (quantum well) / iGaN- skal / nGaN.

Fig. 4A is a schematic view of process integration of III nitride nanowires and III-V nanowires on the same substrate from three separate pieces nanowire plants for an R (III-V) G (III-V) B (III-N) monitor.

Fig. 4B is a schematic view of process integration of two different doped III-V nanowires or silicon nanowires on the same substrate.

Fig. 5A is a schematic view of a CMOS nanostructure with an electric one terminal electrode consisting of cast metal nanoparticles.

Fig. 5B is a schematic view of a CMOS nanostructure with an electric one terminal electrode consisting of single-walled metallic carbon nanotubes grown from nanoparticles incorporated into nanoholes.

Figs. 6A-6G schematically show a process for manufacturing a CMOS nanostructure with two different doped MOS nanostructures according to Fig 5A.

Fig. 7 shows a CMOS nanostructure system where the nanowires have shell layers to configure an anisotropic valence band or to confine electrons in the radial direction of the nanowires by stresses in the crystal structure of undoped heterostructures.

Fig. 8A- Fig. 8E schematically describes a process diagram for manufacturing of nanowire-based solar cells with a number of different doped regions with growth of a plurality of nanowires in different nanowire processes according to the process methodology described in Fig. 6A-6D.

Fig. 9 is a schematic view of a nanowire-based solar cell with a nuclear scale structure, process integration of p-i-n diodes of III-N materials and p-i-n n-diodes of III-V material and a photonic crystal.

DETAILED DESCRIPTION OF THE INVENTION EN An embodiment of the invention relates to a method (1000) for manufacturing a plurality of elongate vertical nanostructures (100, 200, 300, 400, 500, 600, 800a, 800b, 900) on the same substrate (101, 201, 301,401, 501, 601) including; (1001) to provide at least one hole (102, 202, 302, 402, 502, 602, 802a, 802b, 902) in contact with a substrate (101, 201, 301, 401, 501, 601), (1002) to incorporate nanoparticles (103, 203, 303, 403, 503, 603, 803a, 8003b) in at least one of the mentioned holes (102, 202, 302, 402, 502, 602, 802a, 802b) from a nanoparticle suspension which includes an evaporating liquid front (105), and (1003) for heating the said nanoparticles (103, 203, 303, 403, 503, 603, 803a, 803b, 903) in contact with said substrate, preferably over that of the nanoparticles melting point. At least one hole may be covered with an etchable structure (104, 204, 304, 404, 804). Process gases for semiconductor plants can be used during said heating to form said elongate the nanostructures (100, 200, 300, 400, 500, 600, 800a, 800b, 900). The said elongate nanostructures may be III-N nanowires (300) and / or III-V nanowires (400) and / or silicon nanowires (400, 400 ').

The said elongate nanostructures may be metal contacts (500) or metallic carbon nanotubes (600).

Another embodiment of the invention relates to a nanowire component member (4000, 4100, 8000, 9000) including; one first plurality of nanowires (300, 400) and a second plurality of nanowires (400, 800a, 800b, 900), in which said first plurality of nanowires (300, 800a, 800b, 900) comprises at least one pn junction and the said second the plurality of nanowires comprise at least one pn junction, in which the said the first plurality of nanowires and the said second plurality of nanowires are different, in which the said first plurality of nanowires and the said others most nanowires are grown on the same substrate. The first mentioned the plurality of nanowires may comprise pn junctions which are a plurality interconnected p-i-n junctions, and in which the said second the plurality of nanowires include pn junctions which are a plurality interconnected p-i-n junctions. The first majority mentioned nanowires are III-N nanowires comprising at least one quantum well, and the said second plurality of nanowires are III-V nanowires comprising at least one quantum well. The mentioned first plurality of nanowires have substantially different doping from said second plurality of nanowires, preferably the nanowires are p-doped and n-doped, respectively silicon nanowires or III-V nanowires.

Another embodiment of the invention relates to a CMOS nanostructure systems (6000) comprising; a first MOS nanostructure and a second MOS nanostructure, a first and a second all-around gate electrode (5001a), in which the first MOS nanostructure comprises; an n-doped portion of a substrate (501a), an electrical terminal electrode (500a, 500a, 600a, 600b), and a vertically grown p-doped nanowire (400a), in which said n-doped substrate (501a) is in contact with it said p-doped nanowire (400a) and in contact with said the terminal electrode (500a, 600a), and a second MOS nanostructure, in which the second MOS nanostructure comprises a β-doped portion of a substrate (501b), an electrical terminal electrode (500b, 600b) comprising at least one nanoparticle, and a vertically grown n-doped nanowire (400b), and in which said n-doped portion of the substrate (501a) is in contact with said p-doped nanowire (400a) and in contact with it said terminal electrode (500a, 600a), and in which the said p- doped portion of the substrate (501b) is in contact with said n- doped nanowire (400b) and in contact with the said the terminal electrode (500b, 600b), and in which the first p-doped the nanowire (400a) and the other n-doped nanowire (400b) are in electrical contact, in which said first all-around gate electrode (5001a) is in electrical contact with said first β-doped the nanowire (400a) and said second all-around gate electrode (5001b) is in electrical contact with said second n-doped the nanowire (400b).

In the following, the invention will be described in more detail with reference to the accompanying figures, where: Fig. 1A is a process diagram of the method 1000 to be incorporated nanoparticles (103) in nanoholes (102). The process involves drowning the substrate in a particle solution, evaporate a particle solution from the substrate (101), to incorporate a nanoparticle into a nanohole, heat up the substrate (101). In one embodiment, the method is used to grow nanowires (100). In another embodiment, the method 1000 is used for to make terminal contacts (500) into nanowires (400). An advantage of The procedure is to have good control over the nucleation energy for growth the nanowires by regulating the monodisperse size of the gold particles.

Gold nanocolloids can be synthesized by reacting e.g. gold chloride and citric acid. Different types of acids can be used to make different ligands.

The ligands prevent the gold particles from clumping together. An example on a commercial gold nanoparticle suspension manufactured by Ted Pella Inc. with a concentration of 45-1010 gold nanoparticles / mL with tannin ligands. The method uses self-organization with capillary force.

The ligands on the nanocolloids can be broken down thermally or electrically cleaning (electropurification). As an example, citric acid (ligands) an activation energy of 200 kJ / mol for thermal decomposition as shown with thermogravimetry (DSC). The nanoparticles can be of the metals copper, aluminum, nickel, magnesium, palladium, platinum and gold.

The size of the particles can be 2-50 nm (401,402,403). Given cleaning the nanocolloids with electropurification, this does not affect nanowire growth. The nucleation energy decreases at smaller nanowire diameters according to the expression of the chemical potential.

The nucleation energy of the nuclear semiconductor nucleation with the volume of a semicircle with the height of an atomic layer when growing with nanoparticles can written as: A AG (r) = -šrzïu šrza, + r1 “, - where r is the radius of the monolayer, Ap is the difference in chemical potential between a Ga-saturated nanoparticle and the nanowire monolayer, s is the molecular one the area of the region and a, - is a surface energy of the interface between the nanoparticle and the C plane. m) = p .. xGa ZÛ-i Q Ali = AFÅR) = ”nanopartikel _ .unanotråd = kßTln F + R Ga Get A11 Zn: s A Gb rear _ The critical nucleation barrier can be written as: A G Pâ barrier = T Znl s As the radius of the nanoparticle decreases, the driving force for nucleation increases with a low energy barrier similar to the energy barrier for a transition state for a chemical reaction.

The growth rate can be written in monolayer (ML) / min as: Pâ R = R06Xp g.

The nanowire length can be written as Thus, the lengths of the nanowires are determined by the radius of the nanoparticles due to Gibbs-Thomson effects or Laplace printing. The nanowires lengths are determined by the radius of the nanoparticles on the substrate.

Fig. 1B -Fig. 1C describes how a substrate (101) is immersed in beakers with nanoparticles (103). The nanoparticles are incorporated into nanoholes (102) by evaporation of solvent. A liquid front (105) sweeps over the substrate (101) which gives rise to a capillary force.

Fig. 1D shows how nanoparticles (103) have changed position from being located in the nano holes (102) to the top of the elongate nanostructures (100). The nanowires (100) may be silicon nanowires or III-V nanowires. The advantage of the embodiment is that the nanowires become more homogeneous with MOCVD as Ostwald ripening decreases with monodispers diameter of the nanoparticles. The advantage of the embodiment with silicon nanowires is that one can incorporate with the nanocolloids nanoparticles that are compatible with silicon-based CMOS e.g. copper oxide nanoparticles.

Fig. 2 is a schematic figure of nanowires (200) that may be silicon nanowires with nanoparticles (203) at the top of the nanowires (200).

The figure also shows an obstructing plant layer (204). The holes (202) go down to a doped silicon substrate (201). The nanowires (200) are grown from nano holes (202), but may also have been grown out of holes down to the silicon substrate by a AlGaN buffer storage.

Fig. 3A schematically describes a cross section of a hexagonal III-N- nanowire (300) with M-plane facets grown with a nanoparticle (303), seen from the side, on buffer layer with hole (302) down to the buffer layer through a worm. The III nitride nanowires (300) may have the LED structure, seen from inside to outside of a core-shell nanowire; pGaN core wire / pAlGaN- shell / GaN barrier-shell / InXGa1-XN active layer-shell / nGaN barrier-shell / nGaN- shells where the C-plane is the most polar plane of gallium nitride. The C-plane can be most doped in-situ when the nanowire is manufactured. The background doping of gallium nitride is n-type. The advantage of the embodiment is that the p-side of the nanowire is a core wire that is doped in-situ during C-plane growth and that n- the side grows which means that the p-doping can be increased. Each shell layer can be etched in-situ to the same height as the core nanowire so as not to get any luminescence from the C-plane. The advantage of in-situ etched III-N nanowires is that the wavelength becomes more defined as the luminescence differs from those different crystal planes. The advantage of the embodiment is that the p-side of The nanowire (300) is a core wire doped in-situ during C-plane growth and that the n-side grows which means that the p-doping can be increased. High p-doping causes a polarity inversion for Gallium-polar GaN where a high magnesium concentration on the surface is necessary for the polarity inversion and that surface segregation plays an important role, which can be prevented with growth with particle-assisted nanowire plant. When the nanowires (300) grow with use of metal nanoparticles, they are subjected to a capillary shift in it thermodynamic equilibrium between the size of the nanoparticles due of diffusion of metal atoms between the different particles if these from the beginning are different sizes, which is prevented with monodisperse nanocolloids (303).

In-situ etching of gallium nitride on the p-plane in self-catalytic growth can take place takes place according to: Ga + NH3 = GaN + 3/2 H2 there the equilibrium constant of the reaction can be written as 3/2 Kem = <_pßap ~ fl ß) z PHš / Z ZNH3ZG3 where Z. is the partition vibration function of the respective reagent.

The relative supersaturation 1 + v can be written as PGaPNH ~ = <4> V pHä / Z Keqff) If v <0 in-situ, GaN is etched and if v> 0, GaN is deposited.

Fig. 3B is a schematic top view of a hexagonal III-N nanowire (300) with vertical M-plane facets grown with a nanoparticle (303).

The nanowire (300) has a p-doped core wire (310), an intrinsic shell layer on the p-doped core wire (310) and an outer n-doped shell layer (315).

An advantage of the embodiment is that when light reaches the top surface of the nanowire absorbs more sunlight than axially grown nanowires (300) due to the larger surface area of the intrinsic semiconductor layer.

Fig. 3C is a schematic top view of a triangular III-N nanowire (300) plant with a nanoparticle (303). The nanowire has a p-doped core wire (310), an intrinsic shell layer on the p-doped core wire and an outer n-doped shell bearings (315). An advantage of the embodiment is that when light reaches the top surface of the nanowire (300) absorbs a greater amount of sunlight than before axially grown nanowires due to the larger surface area of the intrinsic semiconductor bearings. Another advantage of the embodiment over the core the shell nanowire (300) in Fig. 3B is that the A-plane has higher surface energy than the M-plane plane, which gives higher n-doping of the core wire during growth of the n- doped skull layer. The p-doped core wire (310) may be p-doped with Fig. 3D is a schematic top view of a triangular III-N nanowire (300) with LED structure grown with a nanoparticle. The nanowire has the LED structure pGaN core wire (310) / pA | GaN-ska | (311) / iGaN-ska | (312) / InHGaXN shell (313) (quantum well) / iGaN shell (314) / nGaN (315).

An advantage of the embodiment compared to hexagonal nanowires grown with M-plane facets in Fig. 3B is that the C-plane has the highest growth rate, resulting in higher p-doping of the core wire (310).

Fig. 4A is a schematic view of process integration (4000) of III nitride nanowires (300) and III-V nanowires (400) on the same substrate.

The advantage of the embodiment is that it makes it possible to cover the whole light spectrum to make LEDs (overall) that provide white light on cheap silicon substrate (401). Another advantage of the embodiment is that one does not need to use e.g. a phosphorescent layer which for e.g. blue LEDs to get white light. The nanowires (400,300) can be configured for red and green electroluminescence from III-V nanowires (300) and blue electroluminescence from blue III-N nanowires (300) (note herein as R (III-V), G (III-V), B (III-N). An advantage of the embodiment is that III-N alloys can be combined with III-V alloys to configure bandgap for RGB LEDs. The InHGaXN bandgap is configured for blue electroluminescence and semiconductor alloy AlyGa1-yAsXP1-X are configured for red and green electroluminescence, respectively. The doping atoms from respectively side of the quantum well migrates to the bottom of the quantum well in the diode structure for both positive and negative charge carriers. The advantage of the embodiment is that the said pAlGaN shell (311) helps synergistically to limit the electrons to the InXGaHN quantum well beyond the magnitude effects of the 2-dimensional electron gas for pn- the transition. Another advantage is that when the nanowires (300, 400) grow less than 20 nm, ballistic transport is achieved through the nanowires, which contributes to more energy-efficient LEDs. An advantage of growing core-shell-III- nitride nanowires (300) and III-V nanowires (400) on the same substrate are that it will be possible to make nanowire-based monitors where you grow specific nanowires (300, 400) on different microstatic surfaces. Examples of colors of the electroluminescence are red, green and blue where the blue color comes from nitride nanowires (300) and red and green come from III-V nanowire quantum wells. According to the embodiment, the nanowires (300, 400) grown in falling temperature; III-nitride nanowires (300), then III-V nanowires (400) with gold particles. The III nitride nanowires may have the LED structure seen from the inside to the outside of a core-shell nanowire; pGaN core advice (310) / pAicaw skai (311) / GaN barrier scale) / InXGaHN active layer shell (313) / nGaN barrier shell (314) / nGaN shell (315).

Fig. 4B is a schematic view of III-V nanowires (400) showing process integration (4100) of two different doped III-V nanowires (400, 400 ') on the same substrate. The advantage of the embodiment is that it becomes possible to grow a p-channel as a nanowire (400) and an n-channel as one other nanowire (400 '). Monodisperse nanocolloids (403) can incorporated with a capillary force arising during evaporation of solvent from a nanocolloid suspension by placing the substrate at an angle to the liquid front of the surface (105). Capillary force arises at evaporation of solvent so that the liquid front (105) sweeps over the substrate and incorporates the nanoparticles (403, 403 ') when the substrate is in a beaker of the nanoparticle suspension. The solvent could be ethanol heated on a hot plate.

Fig. 5A is a schematic view of a CMOS nanostructure (5000) having a electrical terminal electrode (500) consisting of molded together metal nanoparticles (503, 503 '). The advantage of the embodiment is that becomes possible to contact the nanowire with the method 1000 with metal nanoparticles. The electrical terminal electrode (500) is vertical perpendicular to the substrate (501) and includes a plurality of nanoparticles (503, 503 ') which are cast together while heating above the melting point (Tm) for the nanoparticles (503, 503 '). The melting point of the nanoparticles (503, 503 ') can be written as; Tm = Tmbulku -I :: S1d), where the melting point is smaller than for the bulk metals for small nanocolloids e.g. 2-5 nm.

Fig. 5B. shows a MOS nanostructure (5000) comprising; at least one single-walled metallic carbon nanotube (600) grown on a substrate (601) by soaking the substrate in a nanoparticle solution, evaporate solvent from the substrate, to incorporate a nanoparticle into one nanoholes with a liquid front (105) and heat the substrate together with process gases for growing carbon nanotubes (600). The mentioned the nanoparticle solution can be cleaned with electric cleaning (electropurification).

A process for growing a nanowire-based CMOS nanostructure system shown in Figs. 6A-6G: Fig. 6A. a) p-dopa and n-dopa a silicon substrate at certain positions. b) Deposit a silicon nitride stop-etch mask, open up all holes with EBL in electron resist or use nanoimprint lithography; and implements a silicon nitride etch with e.g. HF 9 nm / min. c) Open holes in the applied photoresist and deposit SiOX with PEcvo to cover the holes for the upcoming plant (III-v plant # 2). d) Incorporates nanocolloids into the open nano holes with capillary force where the holes are zananocolloid and the holes Fig. 6B. a) Grow the first III-V nanowires (III-V plant # 1) according to existing prescription. b) Coats SiOX over the entire substrate with very little deposition in the holes for III-v-growth # 2.

Fig. 6C. Carry out III-V plant # 2 according to the existing recipe.

Fig. 6D. HF etch away the SiOX cover.

Fig. 6E. a) Grow a thin layer of HfOZ with ALD. b) Sputter on a thin layer of aluminum. c) Spin on polyimide with spin-coating equipment. d) Open holes in polyimide with EBL.

Fig. 6F. a) Etch down the aluminum layer covering the nanowires to the upper edge of the polyimide layer with H3PO4: HNO3: CHgCOOH. b) Etch the HfOZ cover on the nanowires down to the upper edge of the polyimide layer with BCl3 / O2 plasma. c) Etch away the polyimide layer with RIE. d) Deposit a thick layer of HfOZ with ALD to cover the nanowires all the way up to the nanoparticles. f) Use a photoresist and UVL to sputter on a layer of aluminum which forms a contact for the two nanowires in series.

Fig. 6G. a) Deposit a thick layer of silicon nitride as a stop-etch layer to open holes to form contacts to the respective nanowires. b) Open holes in the silicon nitride bearing for each terminal with electron resist with EBL, HF etch 9 nm / min for silicon nitride and continue HF etching through the SiOX layer. Open holes for contact with all-around- the gate electrodes. d) Etch HfO 2 into the holes on the nanowires down to the silicon nitride with BCl3 / O2 plasma. e) HF etch the silicon nitride down to the doped silicon substrate in the holes for the contacts. f) Incorporate metal nanocolloids into the open nano holes with capillary force where rhål> rnanokolloid (This step may need to be iterated). g) Heat the metal nanocolloids over Tm = Tmbulk fl - lfffisld) there the melting point is smaller than for the bulk metals for small nanocolloids e.g. 2-5 nm.

Fig. 7 is a schematic view of a CMOS nanostructure system (6000) with two different doped MOS nanostructures according to Fig. 5A. The advantage with the embodiment is that the CMOS nanostructure system can function as a CMOS inverter with a p-channel and an n-channel, a terminal electrode (5002) connecting the emitters and collectors of the nanowires, but it also has all-around connectors (5001a, 5001b) in electrical series contact for the two nanowires (400a, 400b). The p-doped the nanowire (400a) could be InSb and the n-doped nanowire (400b) can be InAs, InP or GaAs. The mentioned electric the terminal electrodes could be metallic carbon nanotubes (600) grown from incorporated nanoparticles in nanoholes. The graph is metallic and they single-walled carbon nanotubes become metallic when grown in armchair the direction (armchair nanotubes) perpendicular to the zigzag direction there rows of hexagons are bound together along a line. All-around contacts may be graphene etchable with oxygen plasma. The mentioned InAs - the nanowires (400b) may have radii in the range 7-18 nm then electron mobility increases linearly in this range. The straps are bent close to the pn- the transition, but discontinuities in the bands cause charge carriers to be trapped in a potential well near the transition. Tensions have the greatest effects on the band structure near the valence band near F. The bands at stresses in the crystal structure is affected by the voltage which pulls the valence bands apart so that the valence band becomes anisotropic. This can lead to the positive the charge carriers become lighter in the direction of the pn junction. But also the capture of charge carriers contributes synergistically to the same effects as the voltage in the crystal structure from the heterostructure. An advantage of the embodiment is that a larger nanowire diameter can be achieved 1D effects with radial restriction of charge carriers.

Fig. 8A- Fig. 8E schematically describes a process diagram for manufacturing of nanowire-based solar cells (8000) with a number of different doped regions with growth of several nanowires (800a, 800b) in different nanowire processes according to the process methodology described in Figs. 6A-6D with etchable blankets or layers (804a, 804b). The stocks may be SiOx deposited with PECVD and etchable with hydrogen fluoride. Several (6 pieces) different nanowires (800a, 800b) with different p-i-n-diode structures grow on the same substrate (801). An advantage of the embodiment is that it becomes possible to configure the nanowires (800a, 800b) for the entire absorption spectrum for sunlight using different bandgaps with different III-V semiconductors, III- N-semiconductors and / or III-V-N semiconductors. The nanowires (800a, 800b) have heterostructures in their axial direction where the nanowires grow with gold particles (803) incorporated into holes (802). Figures 8A-8C describe how a etching ladder is used to successively etch down SiOx layers from left to right Right. Metal nanoparticles (803) e.g. can be etched away from the nanowires (800a, 800b) peaks, see Fig. 8E.

Fig. 9 is a schematic view of a nanowire-based solar cell (9000) there the nanowires (300, 900) have a core-shell structure. Further describes the figure shows the process integration of p-i-n diodes of III-N material and p-i- n-diodes of III-V material and a photonic crystal (920). The nanowire-based solar cell (9000) includes; at least one III-N nanowire (300) having at least one p-i-n heterostructure in said III-N nanowire radial direction and a III-V nanowire (900) with at least one p-i-n- heterostructure in its radial direction grown on the same substrate (901) and / or at least one III-N nanowire having at least one p-i-n heterostructure in it said axial direction of the III-N nanowire and a III-V nanowire with at least one p-i-n heterostructure in its radial direction grown on the same substrate (901). An advantage of the embodiment is that the light absorption is larger for the nanowire solar cell (9000). The nanowires (300, 900) have p-i-n- diode structure grown in the radial direction and are contacted with around connectors (5001) that completely enclose the nanowires or essentially. A terminal electrode (500) which contacts the all-around the contacts (5001) enable the nanowire-based solar cell (9000) lets in more light. The nanowire-based solar cell may comprise at least a photonic crystal layer (920) that prevents light from passing out solar cells (9000). The photonic crystal layer (920) may be SiOx deposited with PECVD a number of holes in the size 5 nm - 800 nm. The advantage with the embodiment is that a plurality of nanowires with different heterostructures (300,900) and different lattice adjustments for p-i-n- diode structures can be grown and used for nanowire solar cells. Another advantage of the embodiment is that by making tunnel diodes in it radial direction of the pn junctions can be photogenerated electrons tunnel from the pn junction with lower bandgap through the depletion area to the valence band for the pn junction with higher bandgap for a plurality different heterostructures to cover the entire absorption spectrum of sunlight with higher absorption of sunlight in the perpendicular direction to the shells.

Examples of embodiments An example of an embodiment relates to an R (III-V) G (III-V) B (III-N) - monitor comprising; a first set of plant nanowires, a second amount of plant nanowires and a third amount of plant nanowires, in which the said first grown nanowires are III-N nanowires, and in which both the said second nanowires and the said third nanowires are III-V nanowires. The shell layers of the third nanowires can be free framed due to one plant worm to prevent the other the amount of nanowires continues to grow during the growth of the third the amount of nanowires. The III-N nanowires may be configured for blue electroluminescence. The other plant nanowires may be configured for red electroluminescence or green electroluminescence. The third grown the nanowires can be configured for green or red electroluminescence.

Another embodiment relates to an all-around connector manufactured according to the process including; a) to grow a thin layer of HfOZ with ALD. b) sputter a thin layer of aluminum on the hafnium oxide. c) spin on polyimide with spin-coating equipment. d) open holes in polyimide with EBL. e) etch down the aluminum layer covering the nanowires to the upper edge of the polyimide layer with H3PO4: HNO3: CH3COOH. f) etching the HfOZ blanket on the nanowires down to the upper edge of the polyimide layer with BCl3 / O2 plasma. g) deposit a thick layer of HfOz with ALD to cover the nanowires all the way up to the nanoparticles. An advantage of the embodiment is that the nanowires are completely encapsulated to turn the power on and off which flow through the nanowires as p-channels and n-channels, respectively. One another advantage is that the hafnium oxide, with a high dielectric constant, prevents current from flowing between the vertical terminal electrodes and the p-doped and n-doped nanowires, respectively.

An example of an embodiment relates to the process of manufacturing R (III- v) G (111_v) B (111-N) nanowire LEDs: 1. a) Grow a buffer layer of AlN / AlGaN on a silicon substrate and grow one epilager of pGaN on the buffer storage. b) Deposit a silicon nitride stop-etch mask on pGaN, opening up for all holes with EBL in electron resist or nanoimprint lithography; and performs a silicon nitride etch with e.g. HF 9 nm / min. c) Open several first holes in the applied photoresist with UVL and deposit SiOx with PECVD to cover the other holes for plant # 2. d) Opens several third holes in the applied photoresist with UVL and deposits SiOx with PECVD with a thickness greater than for plant # 3. 2. a) Incorporates nanocolloids according to Method 1000 into the open holes. b) Grow III-N nanowires according to existing recipe with covered holes such as to be used for nanowire plant # 2 and nanowire plant # 3. The mentioned The III-N nanowires may have A-plane side facets. 4. a) HF etch the SiOx cover away from the nano holes to be used for plant # 2 where the SiOx cover for nanowire plant # 3 is etched down the same height as for SiOx cover for nanowire plant # 2. b) Coat SiOx over the entire substrate with very little deposition in the holes for nanowire plant # 2. 5. KOH etch down the pGaN and the buffer layer down into the open nano holes down to the silicon substrate. 6. a) Incorporate nanocolloids according to Method 1000 into the open holes. b) Pure the nanocolloids with e.g. heating process, chemical cleaning, chemical reaction or use purified nanocolloids. 7. Perform nanowire plant # 2 with growth of III-V nanowires with core shell-diode structure on the silicon substrate in the open nano-holes with the nanocolloids. The shells of the III-V nanowires grow only on the free part of the nanowires. 8. HF etch the SiOx cover away from the nano holes to be used for the plant # 3. 9. Coat SiOX over the entire substrate with very little deposition in the holes for nanowire plant # 3 to prevent nucleation III-V semiconductors below the nanoparticles used in nanowire plant # 2. (III-V semiconductor does not nucleate on III-N semiconductors and requires a temperature of about 1000 ° C for crystal growth. 10. KOH etch down the pGaN and the buffer layer down into the open nano holes down to the silicon substrate. 11. a) Incorporate nanocolloids according to Method 1000 into the open the holes. b) Pure the nanocolloids with e.g. heating process, chemical cleaning, chemical reaction or using purified nanocolloids. One advantage of using nanocolloids below 5 nm is that each metal nanocolloid is smaller than one grain and that any grain boundaries becomes in the longitudinal direction of the elongate nanostructure. Preferably carbon nanotubes are used as contacts where the carbon nanotubes grow out of the holes from the nanocolloids. 12. a) Carry out nanowire plant # 3 with growth of III-V nanowires with core-shell-diode structure on the silicon substrate in the open nano-holes with the nanocolloids where the lower part of the shells grows at the edge of the SiOx stored. 13. HF etch down the SiOX cover from the upper part of the substrate where the shells on the III-V nanowires become freely framed.

Another example of an embodiment relates to a method of growing nanowire diode structures on a substrate comprising; to provide a substrate comprising nanowires arranged vertically against said the substrate, and at least one pattern with holes in said substrate, in which substrate is soaked in a colloidal nanoparticle suspension, in which nanoparticles from said nanoparticle suspension are incorporated into the said holes by at least one self-organizing means, in which it said at least one self-organizing means comprises a liquid front which sweeps over said substrate by evaporation of solvent to incorporate said nanoparticles into said holes. The said at least one self-organizing means may be a liquid front which sweeps over said substrate by evaporation of solvent to incorporate said nanoparticles into said holes.

Another example of an embodiment relates to a nanowire substrate including; a substrate, an epilayer in the same plane as the said the substrate comprising a first plurality of epitaxially grown nanowires and a second plurality of epitaxially grown nanowires, and wherein the substrate comprises at least one pattern of a plurality of holes in contact with the said the substrate in which the said first nanowires and second the nanowires are arranged perpendicular to said substrate, in which at least the said other nanowires are nucleated from nanoparticles from a colloidal nanoparticle suspension in said one a plurality of holes in which the said nanoparticles are incorporated in the said at least a plurality of holes in contact with said substrate with self-organizing means.

Another example of an embodiment relates to a method of contacting nanowires comprising; to provide at least one hole in contact with one substrate, to incorporate metal nanoparticles into at least one of said the holes in which said nanoparticles are heated above their melting point, in which said molten incorporated nanoparticles are in contact with an n-doped or p-doped portion on said substrate.

Another example of an embodiment is a method of manufacturing elongated vertical nanostructures on a substrate comprising; to provide at least one hole in contact with a substrate, to incorporate nanoparticles in at least one of the said holes to, in which the said the nanoparticles are heated in contact with said substrate, preferably above the melting point of the nanoparticles. At least one hole can be covered with an etchable structure. The mentioned nanoparticles can be selected from the group of copper, platinum, gold, platinum, gold, nickel, cadmium, cobalt and aluminum. The said elongate nanostructures may be III-N- nanowires or III-V nanowires.

The mentioned nanoparticles can form a metal contact. The mentioned the nanoparticles can be cleaned by electric cleaning (electropurification).

Another example of an embodiment is a MOS nanostructure including; a doped substrate, an electrical terminal electrode consisting of of cast metal nanoparticles, and a vertically grown nanowire, in which said doped substrate is in contact with said the nanowire and in contact with said terminal electrode. The said MOS structure may have said nanowire p-doped or n-doped.

In another example of an embodiment, the III-N core wires are grown with nanoparticles, in which the said III-N core wires have A-plane side facets and skull layers have A-plane facets. The advantage of III-N- the nanowires have A-plane facets is that these have a higher growth rate than the M-plane facets, which makes it possible to achieve higher doping. One another advantage of using the A-plane facets is that they nucleate spontaneously with nanoparticle growth compared to self-catalyzed III-N Plant. An advantage of growing nanowires with nanoparticles is that the nanowires nucleat at smaller smaller nanoparticle radii. Another advantage of the embodiment is that the nanoparticles can be grown in order pattern with nanoparticles where the positions of the nanowires are patterned with nanoimprint lithography, without the diameters of the nanowires being determined by the dispersity of the size of the nanoimprint holes.

In one example of an embodiment, the III-N nanowires are grown out of holes defined by nanoimprint lithography. The big difficulty with rlänorråäsväxr is scar get this enough bllllg. Therefore is nanoimprint lithography is a preferred method for both nanowire LEDs and nanowire-p-i-n solar cells.

Another example of an embodiment is the method (1000) of manufacturing elongated vertical nanostructures (100, 200, 300, 400, 500) on one substrates (102, 202,203,204,205) comprising; (1001) to provide at least one hole (102, 202, 302, 402, 502) in contact with a substrate (101, 201, 301, 401, 501), (1002) to incorporate nanoparticles (103, 203, 303, 403, 503) in at least one of said holes (102, 202, 302, 402, 502), and (1003) heating the said nanoparticles (103, 203, 303, 403, 503) in contact with said substrate, preferably above melting point of nanoparticles. At least one hole can be covered with one etchable structure (104, 204, 304, 404). The mentioned oblong the nanostructures may be III-N nanowires (300) and / or III-V nanowires (400). The mentioned holes (201,301,401,501) may be made with nanoimprint lithography. The mentioned oblong the nanostructures may be metal contacts (500).

Another example of an embodiment is a MOS nanostructure (5000) including; a doped substrate (501), an electrical terminal electrode (500) consisting of molded metal nanoparticles, and a vertical plant nanowire (200,300,400), in which said doped substrate (501) is in contact with the said nanowire (200,300,400) and in contact with the said terminal electrode (500). The said nanowire (200) can be p-doped or n-doped.

Another example of an embodiment is a CMOS nanostructure system (6000) including; a first MOS nanostructure (5000a) and a second MOS nanostructure (5000b), and a first and a second all-around gate electrode (5001a), in which the first MOS nanostructure comprises; an n-doped portion of a substrate (501), an electrical terminal electrode (500) consisting of fused metal nanoparticles, and a vertical plant p- doped nanowire (400a), in which said n-doped substrate (501a) is in contact with said p-doped nanowire (200a) and in contact with said terminal electrode (500a), and a second MOS nanostructure (5000b), in which the second MOS nanostructure comprises a p-doped portion of a substrate (501b), an electrical terminal electrode (500b) consisting of molded metal nanoparticles, and a vertical plant n-doped nanowire (400b), and in which said n-doped portion of the substrate (501a) is in contact with said p-doped nanowire (400a) and in contact with said terminal electrode (500a), and in which said p-doped portion of the substrate (501b) is in contact with said n-doped nanowire (400b) and in contact with it said terminal electrode (500b), and in which the first p-doped the nanowire (400a) and the other n-doped nanowire (400b) are in electrical series contact, in which the said first all-around gate the electrode (5001a) is in electrical contact with the said first p- doped nanowire (400a) and said second all-around gate the electrode (5001b) is in electrical contact with said second n- doped the nanowire (400b) and in which the said first all-around the gate electrode (5001a) encloses said first p-doped the middle part of the nanowire (400a) and the said second all-around gate the electrode (5001b) encloses said second p-doped nanowire (400b) middle part.

Another example of an embodiment relates to a MOS nanostructure (5000) including; a doped substrate (501), an electrical terminal electrode (500) consisting of molded metal nanoparticles, and a vertical plant nanowire (200,300,400), in which said doped substrate (501) is in contact with the said nanowire (200,300,400) and in contact with said terminal electrode (500) in which said nanowire may have a plurality of p-i-n layers along the axial of said nanowire direction. The nanowires are grown with the method 1000. The advantage of the embodiment is that it becomes possible to grow a number of different doped nanowires on the same substrate. The nanowires could be configured to absorb shortwave light closest to that of nanowires top and longwave light closest to the bottom of the nanowires.

Another example of an embodiment is a bionanosensor member which includes; one at least one nanowire to be optically driven, the said the nanowire is aligned vertically with a substrate to vibrate freely in the same plane as said substrate, in which the nanowires have one enclosing actuator, in which the nanowire has functionalizing means on its surface, in which the functionalizing means are configured to bind at least one chemical substance.

Another example of an embodiment is a Lab-On-a-Chip system including; a bionanosensor member comprising; at least one nanowire to be operated optically, the said nanowire is arranged vertically against a substrate to vibrate freely in the same plane as the above the substrate, in which the nanowires have an enclosing actuator, in which the nanowire has functionalizing agent on its surface, in which functionalizers, are configured to bind at least one chemical substance, and comprises detecting means for detecting a change of the resonant frequency of at least one nanowire when binding a substance, and includes a laser diode configured to illuminate said the nanowires in a direction towards the substrate to set the said the nanowires in oscillation by flexural dislocation. An advantage of The bionanosensor is a Lab-On-a-Chip system with multiple macro-surfaces for sensor functionality. Another advantage is that the nanowire surface in the form of semiconductor materials can be functionalized.

An example of an embodiment is an optically driven bionanosensor, i which the nanowires are grown in microfluidic channels. The nanowires functionalized by: Spin on electron resist and open up holes in the electron resist with EBL.

Deposit SiOX with PECVD.

Repeat steps 1-2 for k functionalizations.

HF etch down the SiOX cover with the lowest height above the substrate.

Functionalize the nanowires in the microfluidic channels.

Repeat steps 5-6 for k functionalizations.

FhSnPwNl * An advantage of the embodiment is that millions of nanowires can be grown per square millimeters with high dimensional control compared to lithographic defined cantilever liver. Another advantage of the embodiment is that the functionalization of the already previously functionalized nanowires is sterically hindered, which prevents double functionalization.

Another example of an embodiment is a method of manufacturing one bionanosensor member including; to soak a substrate in a nanoparticle suspension, evaporate solvent from the said the nanoparticle suspension from the substrate so that at least one nanoparticle incorporated into a nano hole, grow nanowires with the nanoparticles, and deposit thin films to make an actuator around the nanowire. One another advantage is that the quality factor increases with flexible nanowires on nanoscale as cantilever. Another advantage is that it is recognizable chemical structures in an environment that does not require vacuum. Another advantage is that nanowires can be produced with large-scale production on cheap silicon chips that get a large surface area with sensor functionality. Another advantage is that different nanoparticles can be functionalized with different functionalization means to configure different types of sensors.

Another example of an embodiment for a bionanosensor member such as includes; a plurality of nanowires (100) for optical operation, in which each nanowire is arranged vertically against a substrate (101) to vibrate freely in the same plane as said substrate (101), in which the nanowires have two deposited enclosing propellants, in which they both enclosing propellants have different thermal coefficients of thermal expansion, where one of the propellants is 5 nm chromium and 10-15 nm gold and where the second propellant is piezoelectric silicon nitride where the nanowire is functionalized with at least one chemical ligand bound to the nanowire. The nanowires are synthesized according to one method 1000 and has enclosing drive material around a nanowire.

The advantage of the embodiment is that the nanowires can be produced with large-scale production on cheap silicon chips that have a large surface area with sensor functionality.

Another example of an embodiment relates to a bionanosensor member which includes; a plurality of nanowires for optical operation, in which each the nanowires are arranged vertically against a substrate (101) to vibrate freely in the same plane as said substrate (101), in which the nanowires have two deposited enclosing propellants, i which the two enclosing propellants have different thermal coefficients of thermal expansion, in which the nanowire (100) is functionalized with at least one chemical ligand bound to the nanowire.

The nanowire comprises a nanoparticle (103) at its apex which is chemical functionalized with at least one chemical ligand. The nanowires are synthesized with nanoparticles according to the procedure 1000.

Another example of an embodiment relates to a Lab-On-a-Chip system including; a bionanosensor member comprising; several nanowires (100, 400) for optically operated, in which at least one nanowire is arranged vertically against a substrate (101, 401) to vibrate freely in the same plane as said substrate (101, 401) in which the nanowires (100, 400) has an enclosing actuator, in which the nanowires (100, 400) have functionalizing agent, in which the functionalizing agent is configured to bind at least one chemical substance, and comprises detecting means for detecting a change in the resonant frequency of at least one nanowire when binding a substance, and comprises one laser diode in a direction towards the substrate (101, 401) to set the said the nanowires in oscillation by flexural dislocation by heating.

The nanowires (100, 400) are driven to vibrate at their resonant frequencies. One electrical circuit connected to the nanowire consists of an amplifier to amplify the output signal from the nanowire and have feedback to the nanowire.

The output signal from the nanowire is amplified and goes to a frequency counter.

The frequency counter is connected to a differential circuit. Into the difference circuit there are two inputs, one of which is the signal of the time base. A change in frequency can thus be measured. A drive laser of 432 nm is used to set the nanowires in oscillation. The advantage of the embodiment is that nanowires have been shown to have low bulk modulus at nanoscale diameters for example 20 nm, which means that these are very flexible and not brittle. The allows the nanowires to be driven to strong resonance in liquid at the same time as the measurement accuracy (quality factor) becomes high. The nanowires (100,400) starts oscillating at a resonant frequency. The advantage of the embodiment is that the nanoparticles (103, 403) can be functionalized with different functionalizing agents to obtain different ligands on the nanowires to detect cancer peptides to make cancer tumors detectable in an early treatable stage where the resonant frequency of the nanowire changes upon binding of the cancer peptide.

The quality factor Q can be approximated as: Qwf AfFwHM I where f is the frequency of the amplitude modulated wave from the driving laser and fFWW are the width of the curve at half the maximum value. When a mass loads the nanowire, the initial frequency changes to a final one frequency and mass to an effective mass. For the sake of simplicity can the "spring constant" is not assumed to be changed by the load. Then a relationship can between the effective mass and the final frequency in the respective the old parameters are written as, This relationship holds both in air and in liquid, since the ratio fl / f remains relatively constant for all nanowire lengths. The ratio f '/ f, on the other hand, varies with the width and can not be described entirely by the viscous mass which is attached to the beam but also the displaced liquid must be included in the calculations, which gives: L, I f Inbalk f Inbalk + Invisible + rnundantr _ Given that the new frequency is measured by detection means and it the original resonant frequency of the nanowires is known as well as its mass is known, the effect of the liquid can be determined. A rectangular liquid casing around the beam becomes locked to the movement of the nanowires.

The resonant frequency decreases in liquid, as the surrounding water swings in step with the nanowire. This means a greater effective mass.

Another example of an embodiment relates to a CMOS-based Lab-On-a- Chip systems including; a first MOS nanostructure and a second MOS nanostructure, and a first and a second all-around gate electrode (5001a), in which the first MOS nanostructure comprises; and n-doped part of a substrate (501), comprising an electrical terminal electrode (500) at least one nanoparticle, and a vertically grown p-doped nanowire (400a), in which said n-doped substrate (501a) is in contact with it said p-doped nanowire (200a) and in contact with said the terminal electrode (500a), and a second MOS nanostructure (5000b), i which the second MOS nanostructure comprises a p-doped part of one substrate (501b), an electrical terminal electrode (500b) comprising at least a nanoparticle, and a vertically grown n-doped nanowire (200b), and in which said n-doped portion of the substrate (501a) is in contact with said p-doped nanowire (200a) and in contact with said the terminal electrode (500a), and in which said p-doped portion of the substrate (501b) is in contact with said n-doped nanowire (200b) and in contact with it said terminal electrode (500b), and in which the first p-doped the nanowire (200a) and the other n-doped nanowire (200b) are in electrical series contact, in which the said first all-around gate the electrode (5001a) is in electrical contact with said first p- doped nanowire (200a) and said second all-around gate the electrode (5001b) is in electrical contact with said second n- doped nanowire (200b).

Another example of an embodiment relates to a chemFET nanoelectronics systems including; a first MOS nanostructure and a second MOS nanostructure, and a first and a second all-around gate electrode, in which the first MOS nanostructure comprises; and n-doped part of a substrate, an electrical terminal electrode comprising at least one nanoparticle, and a vertically grown p-doped nanowire, in which the said the n-doped substrate is in contact with said p-doped nanowire and in contact with said terminal electrode, and a second MOS nanostructure, in which the second MOS nanostructure one comprises a p- doped part of a substrate, comprising an electrical terminal electrode at least one nanoparticle, and a vertically grown n-doped nanowire, and i which said n-doped portion of the substrate is in contact with it said p-doped nanowire and in contact with said the terminal electrode, and in which said p-doped portion of the substrate is in contact with said n-doped nanowire and in contact with said terminal electrode, and in which the first p-doped the nanowire and the other n-doped nanowire are in electrical series contact, in which said first all-around gate electrode is in electrical contact with said first p-doped nanowire and it said second all-around gate electrode is in electrical contact with it said second n-doped nanowire, and at least one a bionanosensor member which includes; a plurality of optically operated nanowires, i which at least one nanowire is aligned vertically with a substrate to vibrate freely in the same plane as said substrate, in which the nanowires have an enclosing actuator, in which the nanowires have functionalizing agent, in which the functionalizing agent is configured to bind at least one chemical substance, and comprises detecting means for detecting a change in the resonant frequency of at least one nanowire when binding a substance, and comprises one laser diode in a direction towards the substrate to set the said the nanowires in oscillation by flexural dislocation by heating.

Another example of an embodiment is the method of growing nanowires on plastic substrates including; to spin a polymer layer on a wafer, to spinning silica on said polymer layer, spinning resist on it said silica layer, perform a "lift-off" etching of resist, a nanoimprint stamp makes an impression in the resist, to pattern the said resistant with nanoimprint lithography at room temperature, to etch down resistant to said silica layer, etching away polymer and excess metal by "| ift-off" etching, in which the said the nanoimprint stamp is configured to make a relief pattern in it said resistor being nanoholes in a matrix, and incorporating one nanoparticle in at least one nano hole, and grow at least one nanowire.

Another example of an embodiment is a transparent display including; at least one nanowire LED on a colorless plastic substrate.

The plastic substrate could be a colorless polyimide substrate.

Another example of an embodiment is a nanowire solar cell on one flexible plastic substrate, in which carbon nanotubes are functionalized with porphyrin molecules.

Another example of an embodiment is a mobile telephone which comprises, at least one nanowire solar cell on a flexible substrate, at least one transparent display, at least one self-cleaning surface, in which said substrate can adhere to the growth of vertical nanowires. An advantage of the embodiment is that silicon nanowires or carbon nanotubes can be grown vertically on flexible plastic substrate. Another advantage is that different catalytic nanoparticles can configured to grow nanowires at low temperatures on flexible plastic substrate. Another advantage is that carbon nanotubes can be functionalized with a variety of ligands to make nanobiosensors.

Another example of an embodiment is a method of growing off multiple multiple axial pn junctions along a plurality of nanowires including; depositing a dielectric layer on a substrate having a surface, make at least one hole in said dielectric layer on said substrate, wherein an area at the surface of the substrate is doped, said doped area at the surface of the substrate is centered on the hole and, that arranging a nanowire on the surface of the substrate at a doped portion of one substrate in which said nanowire is substantially in the center line with said doped part of the substrate, forming a first pn junction between said nanowire and said doped portion of the substrate, and to form a second pn junction at nanowires in series connection with said first pn junction; in which the nanowires comprises colloidal nanoparticles, in which the nanoparticles are chemical synthesized from reagents.

An example of an embodiment of the invention relates to a process for grow III-V nanowires with the LED structure Si / pGaP / GaAs / InGaP / nInGaP with the process conditions. A total flow of 13.0 L / min with hydrogen as carrier gas can be used. The mole fractions for PH3, TMG and TMIn can be in the range [2.5-10'5; 6.9> <10 "3].

Another example of an embodiment is a touch screen comprising; one upper layer and a lower layer, in which said upper layer comprises an elongated structure in which said lower layer is a display, and in which said top layer is self-cleaning. The mentioned extended structure can be a nanowire. The touch screen may include rod-shaped polymer lenses configured to scatter light to the right respectively left eye for 3D touch screens. The touch screen technology can be configured to interact with 3D objects displayed on the touch screen.

The touch screen may include an R (III-V) G (III-V) B (III-N) screen. When one users touch the wires bend them and induce a tension. The said nanowires may be connected to CMOS transistors. The advantage using the piezoelectric polymer wires is that these entail a self-cleaning effect at the same time as the threads increase the sensitivity to the screen that is not conditioned on the leading ability of the user fingers. The pressure-sensitive touch screen uses the piezoelectric one the effect compared to resistive and capacitive touch screen technology. When one users touch the microwires or nanowires they bend and they induces a large voltage due to the large number of people touched microwires or nanowires. Another advantage of the pressure sensitive the part is that it gets greater sensitivity and greater accuracy. Another advantage is that the user feels that less pressure is needed compared to it known touch screen technology.

An example of an embodiment of the use of the touch screen is together with a search engine mutatis mutandis that includes 3D objects where a user enters different keywords in a search box, in which "drag-and- drop-objects "are provided on the touch screen as the keywords graphically in a 3D interface. The user can graphically combine different search terms with search operators and exclude keywords from the search by dragging different drag-and-drop objects to the graphical search box. The user can graphically move search terms toward the center of the graphical interface to zoom up prioritize these search terms and move the search terms to the periphery of the touch screen to reduce the priority of these search terms in the search. An advantage of the screen is that a Bayesian search engine can be used where weighting of search terms is given as input to the search algorithm. One another advantage is that the user can graphically combine different search terms with search operators and exclude certain keywords from the search by drag different objects to the graphic search box. The touch screen may include rod-shaped polymer lenses configured to scatter light to the right respectively left eye for 3D touch screens. The touch screen technology can be configured to interact with 3D objects displayed on the touch screen.

An example of an embodiment relates to a touch screen comprising; an upper and a lower layer, in which said upper layer comprises an elongate structure, and a second layer substantially configured as one nanowire-based monitor in which said top layer is self-cleaning. The nanowires give rise to a capillary effect between the threads that grew relatively densely e.g. with a distance of 2 micrometers where liquid is pressed in between the capillaries, which provides a self-cleaning effect. For example, micro-areas may be grown with wires with one diameter of 1-2 micrometers in diameter and a length of 5 micrometers.

The nanowire-based monitor (4000) below the touch screen layer can include rod-shaped polymer lenses configured to scatter light to the right respectively left eye for 3D touch screens. The problems with the known the touch screen technology is i.a. that the touch screens become sticky due to oil from the fingers. Capacitive touch screens can have problems with oil from the fingers of the monitor when it is configured for it human leading ability of the fingers. Capacitive touch screens does not work when the touch screen gets wet or the fingers are damp. Resitive touch screens consist of several layers, which results in poorer image for the screen or the indicator or other display means. Benefits of the embodiment is a touch screen technology that is self-cleaning, larger sensitivity and greater accuracy, nanowires can be coated on nanowire-based LED screens.

In the following, aspects are combined mutatis mutandis as mentioned above features in an embodiment relating to a mobile telephone comprising a transparent touch screen comprising a self-cleaning surface, and comprising piezoelectric microwires or nanowires, in which a layer under the touch screen layer can be configured as a solar cell, and comprising a transparent solar cell layer printed in a plurality of layers configured with at least two different absorption wavelengths for light. When the user touches the wires, bends them and induces a tension, which provides information about the coordinates of a plurality of fingers on the said the touch screen. Ferromagnetic nanoparticles can be used as one fasteners for attaching a flexible monitor and / or cell phone around a wrist. The mobile phone may include the aforesaid cantilever sensor.

An example of an embodiment is a method (1000) for manufacturing one several elongated vertical nanostructures (100, 200, 300, 400, 500, 600) on the same substrate (101, 201, 301,401, 501, 601) comprising; (1001) to provide at least one hole (102, 202, 302, 402, 502, 602) in contact with a substrate (101, 201, 301, 401, 501, 601), (1002) to incorporate nanoparticles (103, 203, 303, 403, 503, 603) in at least one of said holes (102, 202, 302, 402, 502, 602) from a nanoparticle suspension comprising an evaporating liquid front (105), and (1003) heating the said nanoparticles (103, 203, 303, 403, 503, 603) in contact with said substrate, preferably above the melting point of nanoparticles. At least one hole can be covered with an etchable structure (104, 204, 304, 404). Process gases for semiconductor plants can be used during said heating to form the elongate ones the nanostructures (100, 200, 300, 400, 600). The mentioned oblong the nanostructures may be III-N nanowires (300) and / or III-V nanowires (400). The mentioned elongated nanostructures are silicon nanowires (400). The mentioned holes (201,301,401,501) may be made with nanoimprint lithography. The mentioned oblong the nanostructures are metal contacts (500) or metallic carbon nanotubes (600). The said silicon nanowires (201,301,401,501) may include copper oxide nanoparticles.

Another example of an embodiment relates to a MOS nanostructure (5000) including; a doped substrate (501, 601), an electrical terminal electrode (500, 600) comprising at least one nanoparticle, and a vertical plant elongated nanotructure (200,300,400) in which said doped substrate (501) is in contact with said nanowire (200,300,400) and in contact with said terminal electrode (500, 600). The mentioned the terminal electrode (500, 600) may be arranged in an opening for one deposited all-around gate electrode that substantially encloses it said nanowire in a dielectric layer with a high dielectric constant.

Another example of an embodiment relates to a CMOS nanostructure systems (6000) comprising; a first MOS nanostructure and a second MOS nanostructure, a first and a second all-around gate electrode (5001a), in which the first MOS nanostructure comprises; one n-doped part of a substrate (501a), an electrical terminal electrode (500) comprising at least one nanoparticle, and a vertical plant p-doped nanowire (400a), in which said n-doped substrate (501a) is in in contact with said p-doped nanowire (400a) and in contact with said terminal electrode (500a), and a second MOS nanostructure, i which the second MOS nanostructure comprises a p-doped part of one substrate (501b), an electrical terminal electrode (500b) comprising at least a nanoparticle, and a vertically grown n-doped nanowire (400b), and in which said n-doped portion of the substrate (501a) is in contact with said p-doped nanowire (400a) and in contact with it said terminal electrode (500a), and in which said p-doped the portion of the substrate (501b) is in contact with said n-doped the nanowire (400b) and in contact with said terminal electrode (500b), and in which the first p-doped nanowire (400a) and the the second n-doped nanowire (400b) is in electrical contact, in which it said first all-around gate electrode (5001a) is in electrical contact with said first p-doped nanowire (400a) and said the second all-around gate electrode (5001b) is in electrical contact with it said second n-doped nanowire (400b). The two mentioned all-around- the gate electrodes may include an electrical terminal electrode (500c) comprising at least one nanoparticle. At least one of the mentioned nanowires may have a shell layer (7000) to configure at least one anisotropic valence band, preferably to make positive charge carriers lighter or to limit negative charge carriers in the radial direction of the nanowires.

Another example of an embodiment relates to a nanowire-based solar cell (9000) including; a first plurality of nanowires (300, 800a, 800b, 900) and a second plurality of nanowires (900), in which the first nanowire (300, 800a, 800b, 900) has a first plurality of p-i-n junctions and it the second nanowire has a second plurality of p-i-n junctions, in which the first said p-i-n junctions and the other said p-i-n junctions are various. The nanowire-based solar cell may comprise at least one photonic crystal layer (920) comprising nano holes (922). They mentioned several firsts the nanowires (300, 800a, 800b, 900) may be III-V nanowires (800a, 800b) and the other nanowires mentioned are III-V nanowires (900). The said plurality of first nanowires may be III-N nanowires (300) and the other nanowires mentioned are III-N nanowires (300). The said plurality of first nanowires may be III-V nanowires (800a, 800b) and the other nanowires mentioned are III-N nanowires (300). The said III-N nanowires may have vertical A-plane facets or M- plan facets. The said first nanowires and the said second the nanowires can have all-around connectors. Both the III-V nanowires and The III-N nanowires may be grown on a silicon substrate. The mentioned the silicon substrate (901) may be β-doped. The nanowire-based solar cell may include an ITO contact (921). The said all-around electrode (5001) may be substantially deposited as a thin film layer in the same plane as the substrate and enclose the said nanowires in their radial directions. The said nanoholes (922) may be configured in range 50 - 800 nm. The first mentioned a number of nanowires and the said second plurality of nanowires may be core-shell nanowires (300,900).

Another example of an embodiment is a nanowire-based multiple p- i-n solar cell (9000) comprising; a first plurality of nanowires (300, 800a, 800b, 900) and a second plurality of nanowires (900), in which the said the first nanowires (300, 800a, 800b, 900) have a first plurality of p-i-n- transitions and said second nanowires have a second plurality of p-i-n- transitions, in which the said first p-i-n junctions and the said ones the other p-i-n junctions are different. The nanowire-based solar cell can comprise at least one photonic crystal layer (920). The mentioned several the first nanowires (300, 800a, 800b, 900) may be III-V nanowires (800a, 800b) and the mentioned other nanowires are III-V nanowires (900) or the said first plurality of nanowires are III-N nanowires (300) and the said other plurality of nanowires are III-V nanowires (800a, 800b, 900). The nanowire-based solar cell may comprise one doped substrate (901), at least one vertical electrical terminal electrode (500) comprising at least one nanoparticle in which the said doped the substrate (901) is in contact with at least the other plurality of nanowires, and in contact with said terminal electrode (500, 600).

Another example of an embodiment is a CMOS nanostructure system (6000) including; a first MOS nanostructure and a second MOS nanostructure, a first all-around gate electrode (5001a) and a second all-around gate around-gate electrode (5001b), in which the first MOS nanostructure includes; an n-doped portion of a substrate (501a), an electrical elongate terminal electrode (500a, 500a, 600a, 600b) perpendicular to the said the substrate and a vertically grown p-doped nanowire (400a), and in which it said n-doped substrate (501a) is in contact with said p- doped nanowire (400a) and in contact with said elongate the terminal electrode (500a, 600a), and a second MOS nanostructure, in which the second MOS nanostructure comprises a β-doped portion of a substrate (501b), an electrically elongated terminal electrode (500b, 600b) perpendicular to said substrate and a vertically grown n-doped nanowire (400b), and in which said n-doped portion of the substrate (501a) is in contact with said p-doped nanowire (400a) and in contact with it said elongate terminal electrode (500a, 600a), and in which it said β-doped portion of the substrate (501b) is in contact with it said n-doped nanowire (400b) and in contact with said elongated terminal electrode (500b, 600b), and in which the first p-doped the nanowire (400a) and the other n-doped nanowire (400b) are in electrical contact (5002), in which said first all-around gate the electrode (5001a) is in electrical contact with the said first p- doped nanowire (400a) and said second all-around gate the electrode (5001b) is in electrical contact with said second n- doped nanowire (400b).

PREFERRED EMBODIMENTS A preferred embodiment relates to a method (1000) for manufacturing one several elongated vertical nanostructures (100, 200, 300, 400, 500, 600, 800a, 800b, 900) on the same substrate (101, 201, 301,401, 501, 601) including; (1001) to provide at least one hole (102, 202, 302, 402, 502, 602, 802a, 802b, 902) in contact with a substrate (101, 201, 301, 401, 501, 601), (1002) to incorporate nanoparticles (103, 203, 303, 403, 503, 603, 803a, 8003b) in at least one of the mentioned holes (102, 202, 302, 402, 502, 602, 802a, 802b) from a nanoparticle suspension which includes an evaporating liquid front (105), and (1003) for heating the said nanoparticles (103, 203, 303, 403, 503, 603, 803a, 803b, 903) in contact with said substrate, preferably over that of the nanoparticles melting point. At least one hole is covered with an etchable structure (104, 204, 304, 404, 804). Process gases for semiconductor plants can be used during it said heating to form said elongate nanostructures (100, 200, 300, 400, 500, 600, 800a, 800b, 900). The mentioned oblong the nanostructures may be III-N nanowires (300) and / or III-V nanowires (400) and / or silicon nanowires (400, 400 '). The mentioned elongated nanostructures can be metal contacts (500) or metallic carbon nanotubes (600).

Another preferred embodiment relates to a nanowire component member (4000, 4100, 8000, 9000) including; a first plurality of nanowires (300, 400) and a second plurality of nanowires (400, 800a, 800b, 900) in which it said first plurality of nanowires (300, 800a, 800b, 900) comprise at least one pn junction and the said second plurality of nanowires comprises at least one pn junction, in which said first plurality nanowires and the said second plurality of nanowires are different, in which it said first plurality of nanowires and said second plurality nanowires are grown on the same substrate. The first majority mentioned nanowires may comprise pn junctions which are a plurality interconnected p-i-n junctions, and said second plurality nanowires may comprise pn junctions which are a plurality interconnected p-i-n junctions. The first majority mentioned nanowires may be III-N nanowires comprising at least one quantum well, and the said second plurality of nanowires may be III-V nanowires comprising at least one quantum well. The first mentioned most nanowires may have substantially different doping from the above other plurality of nanowires, preferably the nanowires are p-doped respectively n-doped silicon nanowires or III-V nanowires.

Another preferred embodiment relates to a CMOS nanostructure system (6000) including; a first MOS nanostructure and a second MOS nanostructure, a first all-around gate electrode (5001a) and a second all-around gate around-gate electrode (5001b), in which the first MOS nanostructure includes; an n-doped portion of a substrate (501a), an electrically elongated terminal electrode (500a, 500a, 600a, 600b) perpendicular against said substrate and a vertically grown p-doped nanowire (400a), and in which said n-doped substrate (501a) is in contact with said p-doped nanowire (400a) and in contact with it said elongated terminal electrode (500a, 600a), and a second MOS nanostructure, in which the second MOS nanostructure comprises a p- doped part of a substrate (501b), an electrically elongated terminal electrode (500b, 600b) perpendicular to said substrate and a vertical plant n-doped nanowire (400b), and in which said n-doped portion of the substrate (501a) is in contact with said p-doped nanowire (400a) and in contact with said elongate terminal electrode (500a, 600a), and in which said p-doped portion of the substrate (501b) is in in contact with said n-doped nanowire (400b) and in contact with said elongate terminal electrode (500b, 600b), and in which the first p-doped nanowire (400a) and the second n-doped the nanowire (400b) is in electrical contact (5002), in which the said the first all-around gate electrode (5001a) is in electrical contact with it said first β-doped nanowire (400a) and said second universal the around-gate electrode (5001b) is in electrical contact with the said other n-doped nanowires (400b). Although modifications and changes may be suggested by those skilled in the art the area or areas, it is the intention of the inventor to within the scope for what is described herein, that the round of protection includes all changes and modifications that reasonably and correctly fall within the scope of the scope of protection covered by the described contribution to the position or the positions. The present invention according to the appended claims the claims have been described above with reference to specifics embodiments. For example, different features of embodiments combined in combinations other than those described mutatis mutandis.

The scope of the invention is limited only by the appended claims.

Claims (10)

PATENT REQUIREMENTS A method (1000) for manufacturing a plurality of elongate vertical nanostructures (100, 200, 300, 400, 500, 600, 800a, 800b, 900) on the same substrate (101, 201, 301,401, 501, 601) comprising; (1001) providing at least that holes (102, 202, 302, 402, 502, 602, 802a, 802b, 902) in contact with a substrate (101, 201, 301, 401, 501, 601), (1002) that incorporate nanoparticles (103, 203, 303, 403, 503, 603, 803a, 8003b) in at least one of said holes (102, 202, 302, 402, 502, 602, 802a, 802b) from a nanoparticle suspension comprising an evaporating liquid front (105), and (1003) heating the said nanoparticles (103, 203, 303, 403, 503, 603, 803a, 803b, 903) in contact with said substrate, preferably above the melting point of the nanoparticles. The method (1000) of claim 1, wherein at least one hole is covered with an etchable structure (104, 204, 304, 404, 804). The method (1000) of claims 1 and 2, wherein semiconductor plant process gases are used during said heating to form said elongate nanostructures (100, 200, 300, 400, 500, 600, 800a, 800b, 900). The method (1000) of claims 1-3, wherein said elongate nanostructures are III-N nanowires (300) and / or III-V nanowires (400) and / or silicon nanowires (400, 400 '). The method (1000) of claims 1-4, wherein said elongate nanostructures are metal contacts (500) or metallic carbon nanotubes (600). A nanowire component member (4000, 4100, 8000, 9000) comprising; a first plurality of nanowires (300, 400) and a second plurality of nanowires (400, 800a, 800b, 900), wherein said first plurality of nanowires (300, 800a, 800b, 900) comprise at least one pn junction and said second the plurality of nanowires comprise at least one pn junction, in which said first plurality of nanowires and said second plurality of nanowires are different, in which said first plurality of nanowires and said second plurality of nanowires are grown on the same substrate. The nanowire component member (8000, 9000) according to claim 6, wherein said first plurality of nanowires comprises pn junctions which are a plurality of interconnected pin junctions, and wherein said second plurality of nanowires comprises pn junctions which are a plurality of interconnected pin transitions. The nanowire component member (4000) of claim 7, wherein said first plurality of nanowires are III-N nanowires comprising at least one quantum well (313), and said second plurality of nanowires are III-V nanowires comprising at least one quantum well. A nanowire component member (4100) according to claims 6-7, wherein said first plurality of nanowires have substantially different doping from said second plurality of nanowires, preferably the nanowires are p-doped and n-doped silicon nanowires or III-V nanowires, respectively. A CMOS nanostructure system (6000) comprising; a first MOS nanostructure and a second MOS nanostructure, a first all-around gate electrode (5001a) and a second all-around gate electrode (5001b), in which the first MOS nanostructure comprises; an n-doped portion of a substrate (501a), an electrically elongated terminal electrode (500a, 500a, 600a, 600b) perpendicular to said substrate and a vertically grown p-doped nanowire (400a), and in which said n-doped the substrate (501a) is in contact with said p-doped nanowire (400a) and in contact with said elongated terminal electrode (500a, 600a), and a second MOS nanostructure, in which the second MOS nanostructure comprises a p-doped part of a substrate (501b), an electrically elongated terminal electrode (500b, 600b) perpendicular to said substrate and a vertically grown n-doped nanowire (400b), and in which said n-doped part of the substrate (501a) is in in contact with said p-doped nanowire (400a) and in contact with said elongated terminal electrode (500a, 600a), and in which said p-doped portion of the substrate (501b) is in contact with said n-doped nanowire ( 400b) and in contact with said elongate terminal electrode (500b, 600b), and in which the first p-doped nanowire (400a) and the second n-doped nanowire (400b) are in electrical contact (5002), in which said first all-around-gate electrode (5001a) is in electrical contact with said first p doped nanowire (400a) and said second all-around gate electrode (5001b) are in electrical contact with said second n-doped nanowire (400b).