SE1150594A1 - Short-circuit reduction in an electronic component, comprising a stack of layers arranged on a flexible substrate - Google Patents

Abstract

26 ABSTRACT An electronic component (1) and an electronic device (100) comprisingone or more such components (1). The electronic component (1) comprises astack (4) of layers arranged on a flexible substrate (3). Said stack comprisesan electrically active part (4a) and a protective layer (11) for protecting theelectrically active part against scratches and abrasion. Said electrically activepart comprises a bottom electrode layer (5) and a top electrode layer (9) andat least one insulating or semi-insulating layer (7) between said electrodes.The stack further comprises a buffer layer (13), arranged between the topelectrode layer (9) and the protective layer (11). The buffer layer (13) isadapted for at least partially absorbing a lateral dimensional change (AL)occurring in the protective layer (11) and thus preventing said dimensionalchange (AL) from being transferred to the electrically active part (4a), therebyreducing the risk of short circuit to occur between the electrodes. Elected for publication: Fig. 2c

Description

SHORT CIRCUIT REDUCTION IN AN ELECTRONIC COMPONENTCOMPRISING A STACK OF LAYERS ARRANGED ON A FLEXIBLESUBSTRATE Technical field The present disclosure relates generally to an electronic componentcomprising a stack of layers arranged on a flexible substrate, wherein saidstack comprises an electrically active part and a protective layer for protectingthe electrically active part against scratches and abrasion, and wherein saidelectrically active part comprises a bottom electrode layer and a top electrodelayer and at least one insulating or semi-insulating layer separating said electrodes.

Technical backgroundConventionally, electronic components are typically provided on rigid substrates, such as silicon. However, electronics become increasingly usedalso in non-conventional application areas and new technologies emerge forproducing electronics, where use of flexible substrates is desirable or evenrequired. This is for example the case for printed electronics, where use of aflexible substrate may be desirable or even required from manufacturing,application area, and/or cost perspectives.

Printed electronics may replace conventional electronics in case ofvery simple components, which can be realized less expensive by printingtechnologies; however, the aim is typically new application areas whereconventional electronics are not suitable for technological or cost reasons.Applications for printed electronics involve, for example, tags and labels inwhich information can be stored. ln such applications, and in principle in anyelectronic device, availability of memory components is crucial.

The present applicant has presented a memory technology that can be realized by printing processes, which e.g. is described in WO2006/135246.

The memory is based on a ferroelectric material as the memory substance, in 2 particular a ferroelectric polymeric material. Memory materials of this kind hasproven to be rewritable and bistable over prolonged periods of time. Eachmemory cell is a capacitor-like structure where the memory material is locatedbetween a pair of electrodes and where the memory cell is accessed viaconductors linking the electrodes to electronic driver or detection circuitry.The latter may e.g. be located on the periphery of the memory array or on aseparate module. Depending on the application, memory device may containfrom one individual memory cell and up to several millions of cells arranged inmatrix arrays. Some basic cell architectures and array arrangements areschematically shown in Figs. 1a-d. lt may be noted that the substrate is notshown, only the electrically active part of the memory cells. Each cell can beviewed upon as a sequence, or stack, of layers arranged on the flexiblesubstrate, the stack involving at least one electrically active part comprisingtwo electrode layers (top and bottom) with a layer of the (insulating) memorymaterial arranged in-between.

When fabricating ferroelectric memory cells of capacitor type it isevidently important to avoid shorts through the memory cells. Shorts are heredefined by a conducting or low resistance path, compared to a desired normalsituation, from one of the electrodes to the other electrode. The short circuitsare detrimental to the memory cell function as they can both hide the datacontent of a memory cell and also deteriorate the writing of data into thememory device. The problem with shorts is typically greater when thememory material layer between the electrodes is thin. However, the thicknessof the memory layer and drive voltage are typically proportional to each other,and in order to meet up with low voltage requirements, there is often no otheroption than using a thin memory layer. Manufacturing will always lead tosome extent of memory cells being short circuited or more prone to be shortcircuited. lt is desirable to reduce the risk of short circuits to occur.

Furthermore, printed electronic devices or components typically needto be protected against external influences, such as physical damage, but it istypically not possible, nor desirable with protection by e.g. encapsulation as inconventional electronics. lnstead a desirable type of protection is an outer protective layer terminating the stack and that adds protection by e.g. 3 providing scratch and abrasion resistance and resistance against detrimentalenvironmental influence. A protective layer of this kind can be provided as aglobal layer covering multiple memory cells, e.g. by completely covering aprinted memory device. Such protective layer typically need to be hard andrelatively thick, such as in a range of 2-20 micrometers, and it is often suitableand desirable to use a material that can be deposited as layer in a fluid stateand then hardened, e.g. by using a UV curable varnish as the protection layer.

Summarv of the invention ln view of the above, an object of this disclosure is to present a solutionovercoming or at least alleviating problems in the prior art, or to at leastpresent an alternative solution. A more specific object is to provide a solutionthat enables reduction of the number of shorts that may occur in memory cellsof the above described type, that is, memory cells comprising a stack oflayers arranged on a flexible substrate, where said stack comprises a bottomelectrode layer and a top electrode layer separated by an organic memorymaterial and where the stack is terminated by a protective layer.

The invention is defined by the appended independent claims.

From extensive testing and investigation of memory devices and cellsof the above described type, in particular such realized as printed electronics,the applicant has, among other things, found that use of a protective layerthat is hardened after deposition, increases the risk of shorts to occur.

Although there is no wish to be bound by a particular theory ofunderlying causes to the observed phenomena, one explanation may bedimensional change, such as shrinking, of the protective layer resulting fromthe hardening. Although commerclally available materials, as known by theskilled person, for provision of such protective layers often strive towards aslow dimensional change as possible and may reach as low as only about 1%change in size, it may be extremely hard, if at all possible, to totally avoiddimensional change in such layers. By the adhesion of the protective layer tothe underlying stack, the dimensional change transforms into lateral forcesacting upon and stressing the underlying layers, including the memory cell. ln 4 order to be flexible, a flexible substrate apparently has to be thinner than arigid-substrate if they are made of the same material, or, be made of a softermaterial (e.g. by having a lower glass transition temperature Tg) if made ofdifferent material than a rigid substrate of same thickness. ln both cases it isunderstood that the flexible substrate contributes with less resistance tolateral forces than a rigid substrate, whereby the layers of the memory cell willbe subject to greater stress. The problem may be particular prominent whenlateral dimensions of a memory cell, typically defined by the lateral dimensionof electrode crossings of a memory cell, are magnitudes greater than thethickness of the layers, since then already a few percentage of lateraldimensional change may correspond to a vertical “through layer” dimensionalchange that in size is greater than the thickness of the memory layer. Suchratios, i.e. when lateral dimensions of a memory cell are magnitudes greaterthan the vertical dimension, are typically the case for printed memory cells.Also, the force resulting from the dimensional change of the protective layerand that act on the rest of the stack through the adhesion of the protectivelayer, typically increases with the thickness of the protective layer, and, sincethe protective layer often has to have a thickness that is magnitudes greaterthan the thickness of electrically active part of the memory cell (the electrodesand the memory layer), and often in the same order of size as the substratethickness, it may be particular difficult for these layers and the substrate toresist such force. For example, a printed memory cell may have electrode andmemory layers that have thicknesses that are fractions of a micrometer, thethicknesses of the protective layer and the substrate may be manymicrometers thick, and the lateral dimensions of the memory cell more thanhundred micrometers. When the memory film and/or the electrodes, owing tothe use of flexible substrate, to a greater extent become loaded by forcescaused by dimensional change in the protective layer, the risk increases thatthese layers deform, locally crack and/or that the topography increase, theresult in any case being increased risk that protruding parts or fragments ofthe electrodes penetrates the memory material and cause short circuit or that small fragments or structures are formed where the electric field strength will 5 be so high when the memory cell is electrically operated that there literally willbe microscopic explosions in the memory cell, resulting in short circuit.

The described problems may exist also for other electroniccomponents that have a similar structure as the memory cells, in particular forother electronic components realizable by printing technologies.

Hence, according to a first aspect there is provided an electroniccomponent comprising a stack of layers arranged on a flexible substrate,wherein said stack comprises an electrically active part and a protective layerfor protecting the electrically active part against scratches and abrasion. Saidelectrically active part comprises a bottom electrode layer, a top electrodelayer and at least one insulating or semi-insulating layer between saidelectrode layers. The stack further comprises a buffer layer arranged betweenthe top electrode layer and the protective layer, the buffer layer being adaptedfor at least partially absorbing a lateral dimensional change occurring in theprotective layer and thus preventing said dimensional change from beingtransferred to the electrically active part. ln view of the above, by the absorption of lateral dimensional change,the electrically active part is to a reduced extent exposed to forces caused bythe lateral dimensional change, e.g. caused by shrinkage during curing, of theprotective layer, and thus the risk for deformations in the electrically activepart is reduced and by that the risk of short circuit is reduced as well.

By “short circuit” is here meant a conducting or low resistance path,compared to a desired normal situation, from one electrode to the otherelectrode, which is detrimental to the functioning of the electronic component.

By “electrically active part” is here meant the parts of the stackproviding the electrical function of the electrical component. The protectivelayer and the buffer layer are thus not required for the electrical function of theelectrical component.

By “lateral” is here meant in the plane of the layer or in a direction in aplane parallel to the major surfaces of the layer, as opposed to a vertical ororthogonal direction.

By “flexible substrate” is here meant capable of significant bending,such as following the curvature of a curved object, e.g. a drum, comparatively 6 easily and without breaking, as opposed to a rigid substrate, such as ofsilicon.

By “adapted for at least partially absorbing a lateral dimensionalchange” is here meant that the buffer layer is made of a material and hasdimensions and other Characteristics allowing lt to absorb the dimensionalchanges to a sufficient extent.

The at least partial absorption of the lateral dimensional change maycomprise absorbing the lateral dimensional change by at least 99%, or by atleast 95%, or by at least 90%, or by at least 80%, or by at least 50%, or by atleast 30%.

The buffer layer may be adapted for at least partially absorbing thelateral dimensional change by being of a coherent material and having suchlayerthickness that a lateral dimensional deformation in a top portion of thebuffer layer facing the protective layer results in substantially less lateraldimensional deformation in a bottom portion facing the electrically active part,when said lateral dimensional deformation in the upper part is caused by thelateral dimensional change of the protective layer. The difference in lateraldeformation between the top and bottom portions may correspond to theabsorbed lateral dimensional change. ln this embodiment, the buffer layerthus absorbs the lateral dimensional change in the protective layer by thedeformation in the upper portion, which strongly reduces force transfer to theunderlying layers, including the electrically active part. lt is understood thatthe reduction become stronger by a thicker buffer layer, but that too thicklayers often are undesirable for other reasons, as realized by the skilledperson.

By “substantially less lateral dimensional deformation in the bottomportion” is typically meant that less than one percent of lateral dimensionaldeformation in the top portion should manifest as deformation in the bottomportion.

The lateral dimensional deformation in the upper part may be asubstantially completely elastic deformation.

The buffer layer preferably comprises, or substantially consists of, amaterial with a glass transition temperature Tg that is lower than 30 degrees C 7 or preferably lower than 25 degrees C. A glass transition temperature suchlow defines a group of materials that has the ability to provide the at leastpartly absorption of the lateral dimensional change in the protective layer.Such material is typically polymeric and may further provide the buffer layerwith ability to also at least partly absorb dimensional changes in a directionperpendicular to a direction of the lateral dimensional change, i.e. mayprovide the buffer layer with a property to absorb dimensional change in alongitudinal direction, that is, in a “through layer” direction. Such absorptionmay also reduce impact from the above-mentioned microscopic explosions byproviding a buffer means for the explosive forces and vertical deformationsthat else would be confined only to the electrically active part by the protectivelayer. Compare e.g. to the situation with an explosion of same strength in asmall or in a spacious room, or in a can with or without a lid. Hence, if the“lateral absorption” may reduce the risk of high field strength fragments orstructures to form in a first place, i.e. embryos that may cause themicroscopic explosions, the “vertical absorption” reduces the risk of suchfragments or structures that nevertheless are formed, or that are alreadypresent of other reasons, to cause short circuit.

The material of the buffer layer may be a hybrid material comprising atleast one material component that has a glass transition temperature Tg thatis lower than 30 degrees C or preferably lower than 25 degrees C.

By “hybrid material” is here meant a material that comprises more thanone material component, where the components typically havedistinguishable glass transition temperature peaks. Said at least one materialcomponent may be a material component that connects material pieces ofanother material component that have higher glass transition temperature,which e.g. may be above 30 degrees C.

The at least one material component may constitute at least 50%, or atleast 80%, or at least 90%, of the hybrid material. The hybrid material mayhave several glass transition temperatures, one for each material component.The at least one material component with a glass transition temperature ofless than 30 degrees C, may constitute a dominant part of the hybrid material.The buffer layer as whole may thereby get the desired properties. 8 The buffer layer may comprise, or substantially consist of, a materialwith a glass transltion temperature (Tg) that is higher than -130 degrees C orpreferably higher than -90 degrees C.

The buffer layer may comprise, or substantially consist of, a materialor mix of two or more materials from any one of the following: silicon rubber,natural rubber, polypropylene glycol, polyvinyl acetate and acrylate basedresins.

The buffer layer may have a thickness in a range of 1 to 40 um.

The electronic component may be a ferroelectric memory cell whereinthe insulating or semi-insulating layer is a layer of ferroelectric memorymaterial, preferably an organic, such as a polymeric, ferroelectric memorymaterial.

The lateral dimensional change of the protective layer may be suchcausable by hardening of the protective layer, such as by curing, or bytemperature differences in an operational temperature interval of theelectronic component, such as -10C to +50C. The lateral dimensional changeof the protective layer may be about or below 3%, preferably about or below2%, more preferably about or below 1%, in any lateral direction.

The electrically active part and/or the buffer layer may have beenprinted on the flexible substrate.

The protective layer may be directly attached to the buffer layer. ltshould be noted that it in some embodiments may be an intermediate layer orlayers arranged between the buffer layer and the protective layer.

The protective layer may comprise a material that has been hardened,such as by means of curing, after it has been deposited on the stack.

The protective layer may comprise a protective film and an adhesiveattaching the protective film to the buffer layer, wherein the adhesive may bethe material that has been hardened.

The protective layer may be in the form of a protective film and thebuffer layer may form an adhesive attaching the protective film to the rest ofthe stack.

The buffer layer may be formed of a non-coherent material confinedbetween the protective layer and the top electrode layer. 9 By “non-coherent material is here meant that the material consists ofelements that are not or so weakiy bound to each other that it is possible tomove some particles in one surface of the layer without causing movement of,or cause a force to act upon, elements in the opposite surface. Hence, anyforce, such as caused by lateral dimensional change in the protective layer,acting upon elements in a buffer layer surface facing the protective layer, maymove those particles and possibly some neighbour particles, but will not resultin any significant force acting upon a particle in an opposite surface of thebuffer layer, and thus no, or reduced, force from lateral dimensional change ofthe protective layer will load the underlying layers. The non-coherent materialwill thus absorb any lateral dimensional change in the protective layer.

The non-coherent material is may be a gas, and the buffer layer maycorrespond to a gas filled gap, such as a gap filled with carbon dioxide or anair-gap.

According to a second aspect there is provided use of a buffer layer forreduction of short circuits in an electronic component, where the buffer layerand the electronic component may be such as discussed in the foregoing.

According to a third aspect there is provided use of a material with aglass transition temperature Tg that is lower than 30 degrees C, or preferablylower than 25 degrees C, for forming a buffer layer for reduction of shortcircuits in an electronic component. The buffer layer and the electroniccomponent may be such as discussed in the foregoing.

According to a fourth aspect there is provided a method for producingan electronic component comprising a stack of layers arranged on a flexiblesubstrate where said method comprises: providing said substrate andarranged thereon an electrically active part of said stack, where theelectrically active part comprises a bottom electrode layer and a top electrodelayer separated by at least one insulating or semi-insulating layer; andproviding a protective layer for protecting the electrically active part againstscratches and abrasion. Wherein the method further comprises one or both ofthe following steps: providing a buffer layer on top of said electrically activepart of said stack before providing the protective layer, wherein the buffer layer may be such as discussed in the foregoing, and/or electrically operatingthe electrically active part before providing the protective layer.

When electrically operating the electrically active part, small fragmentsor structures that have been formed in the electrically active part, e.g. owingto an uneven substrate or other imperfections, may receive so high electricfield strength that there literally will be microscopic explosions in theelectrically active part, as discussed in the foregoing. lf a hard protection layerat that point is present, the micro explosions are taken part in a rather smallvolume and are confined to the electrically active part, resulting in increaseddamage and increased risk of shorts to occur. lf the micro explosions aretriggered without presence of the protective layer, the damage may become isless and thereby there is less risk of shorts to occur. The buffer layer, asdiscussed above, may reduce the risk of micro explosion embryos to form in afirst place. The buffer layer, owing to that it is must typically be made of amuch softer material than the protection layer, may also act as a buffer formicro explosions that are nevertheless taking part, reducing the damage suchmicro explosions may have on the electrically active part.

The step of providing the protective layer may involve depositing alayer in a fluid form and subsequently hardening the deposited layer, such asby curing. lf providing the protective layer involves subsequent hardening, thestep of electrically operating may be performed after deposition but before thehardening. Only after it has hardened the protective layer may direct theeffect of any micro explosion towards the electrically active part and result ina more closed volume in which any microscopic explosion may cause greaterdamage.

According to a fifth aspect there is provided an electronic device comprising one or more electronic components as discussed in the foregoing.

Brief description of the drawinqs The above, as well as other aspects, objects and advantages of thepresent invention, will be better understood through the following illustrativeand non-limited detailed description, with reference to the appended schematic drawings. 11 Fig. 1a schematically illustrates a cross section view of an exemplifyingprior art memory cell.

Fig 1b schematically shows a top view of an exemplifying prior artmemory device comprising an array of memory cells.

Fig. 1c schematically illustrates a top view of an exemplifying prior artmemory device comprising memory cells arranged in a matrix.

Fig. 1d schematically illustrates a cross section view of the memorydevice shown in Fig. 1b or 1c.

Fig. 2a schematically shows a cross section of a memory cellaccording to one embodiment having reduced risk of shorts to occur.

Fig. 2b schematically shows a cross section of a memory deviceaccording to one embodiment.

F ig. 2c schematically illustrates deformation in a buffer layer of thememory cell according to the embodiment in Fig. 2a.

Fig. 3 schematically shows a cross section of a memory cell accordingto another embodiment having reduced risk of shorts to occur.

Fig. 4 is a flow chart illustrating a method for reducing the risk of shortcircuits to occur in an electronic component, such as a memory cell. ln the drawings the same reference numerals may be used for same,similar or corresponding features, even when the reference numerals refer to features in different embodiments.

Detailed descriptionFig. 1a schematically illustrates a cross section view of an exemplifying prior art memory cell 1, illustrating a generic structure of such memory cell.The memory cell in question comprises a pair of electrodes in the form oflayers 5,9 contiguous to a volume of an electrically polarizable substance,typically in the form of a ferroelectric memory material layer 7. Typically thememory cell 1 has a parallel-plate capacitor~like structure as shown. Thissimple structure is in strong contrast to memory cells in traditional memorytechnologies, where one or more transistors or other semiconductingelements are required in association with each cell, and the consequences for low cost manufacturing are dramatic. A plurality of such memory cells 1 may 12 be arranged side by side on a common substrate (not shown in Fig. 1a), eachcell having the generic structure shown in Fig. 1a, where electrical access toeach cell may be by wire connection to each of the two electrodes.Depending on the application, the size, shape, spatial distribution, andelectrical connection arrangement for a plurality of memory cells 1 may vary.ln cases where a memory device 100 as shown in Figs. 1b-c involves a largenumber of memory cells, a matrix or array of memory cells 1 provides asimple and compact means of providing electrical access to individual cells 1for writing, reading, and erasing operations. This memory device configurationis often termed a passive matrix device since there are no switchingtransistors present for switching a memory cell on and off in an addressingoperation. Basically a memory device 100 of this kind is formed with a firstpattern of parallel strip-like electrodes, corresponding to bottom electrodes 5,which is located on a common substrate (not shown) and covered by a globallayer of ferroelectric memory material 7 e.g. a ferroelectric polymer, overwhich is provided another electrode pattern comprising likewise parallel strip-like electrodes, corresponding to top electrodes 9, but oriented orthogonally tothe first electrode pattern, so as to form an orthogonal electrode matrix. Theferroelectric memory material may also be applied as a non-continuous layer,i.e. a pattern, forming a layer at each individual memory cell but not globally.The first electrode pattern, or set of electrodes 5, can e.g. be regarded as theword lines of a matrix-addressable memory device, while the secondelectrode pattern, or set of electrodes 9, can be regarded as the bit linesthereof. At the crossings between the word lines and bit lines, the memorycells 1 are defined in the matrix, each cell 1 thus having a vertical, or stackedstructure as shown in Fig. 1a, comprising a bottom electrode layer 5 and topelectrode layer 9 with a ferroelectric memory material layer 7 in-betvveen.Each memory cell is laterally confined by the electrode crossing area, or, incase of a patterned memory material layer, by the lateral extension of thememory material at such crossing.Fig 1b schematically shows a top view of an exemplifying prior art memory device 100 comprising an array of memory cells 1, each having the cross-sectional structure described above in connection with Fig. 1a. There is 13 one common bottom electrode 5, but each memory cell has a separate topelectrode 9. The memory material is provided as a global layer 7 between thebottom and top electrodes, each memory cell 1 being formed at the crossingbetween the bottom electrode 5 and the respective top electrode 9. Theelectrodes may as shown be drawn to outside the area where the memorycells 1 are located, and a respective contact pad may be located at the end ofeach electrode for external electrical contacting of the electrodes, for examplein order to read and/or write the memory cells by means of external circuitry.

Fig. 1c schematically illustrates a top view of an exemplifying prior artmemory device comprising memory cells 1 arranged in a matrix. Thestructure is an extension of the structure shown in Fig. 1b, with multipleparallel bottom electrodes 5 in addition to the top electrodes 9, each electrodebeing common for all memory cells 1 in a row or column. The memorymaterial is provided as a global layer 7 between the top and bottomelectrodes 5,9 and respective memory cell 1 is formed at the crossings of thebottom and top electrodes 5,9.

Fig. 1d schematically illustrates a cross section view of a memorydevice 100 as shown in Fig. 1b or 1c, one memory cell 1 being highlightedand marked with a dashed square to facilitate comparison with the genericstructure shown in Fig. 1a.

The arrayed memory cells 1 on a given substrate may be electricallyaccessed from external circuitry, e.g. by means of mechanical contacts padson the substrate. Such solutions are e.g. disclosed in WO2006/135247 andWO2006/135245. Alternatively, there may be active electrical circuitryincorporated on or in the substrate itself. The circuitry may be located in thinfilm semiconducting material based on silicon (amorphous or polycrystalline)or organic materials (polymers or oligomers). When the memory cells areprintable, for example such as described in WO2006/13524, the circuitry ispreferably printable as well.

Substrates, onto which the memory cells discussed above and in thefollowing are typically flexible. They may be electrically insulating, e.g. in theform of a sheet of paper, a plastic foil, glass, board, carton or a compositematerial of any of these materials. Alternatively, they may be electrically 14 conducting, e.g. in the form of a metal foil with an insulating coating to avoidelectrical short circuits.

Electrodes discussed above and in the following may be of metal,preferably from printable metal inks, but can alternatively be e.g. conductingorganic material, such as of a conducting polymer, e.g. PEDOT, preferablyalso printable. Also other organic or inorganic materials may be used andpreferably such that are printable.

The ferroelectrlc memory material discussed above and in thefollowing, is preferably organic, such as one of an oligomer, copolymer, orterpolymer, or a blend or composites thereof. lt may preferably be acopolymer of polyvinylidene fluoride and trifluoroethylene (P(VDF-TrFE)).

Memory cells 1 and memory devices 100 according to variousembodiments will be discussed in the following. As will be recognized, theembodiments may be viewed upon as extended versions of the memory cells1 and memory devices 100 discussed in the foregoing, where the memorycells and devices discussed in the foregoing correspond to electrically activeparts of the embodiments.

Fig. 2a schematically shows a cross section of a memory cell 1according to one embodiment having reduced risk of shorts to occur. Thememory cell comprises a stack 4 of layers on a flexible substrate 3. Theflexible substrate 3 may have a thickness in a range of about 10 pm to 300um. The flexible substrate 3 is preferably made of any one of: PolyethyleneNaphthalate (PEN), Polyethylene Terephthalate (PET), Polyimide, Polyether(PE), Polyvinyl chloride (PVC), Polycarbonate (PC), Polyethylene (PE), or thelike. The stack 4 of layers comprises an electrically active part 4a which is thepart that provides the electrical function, here the electrical function of thememory cell 1. The electrically active part 4a may correspond to a prior artmemory cell 1 as discussed above in connection with Fig. 1.

Fig. 2b schematically shows a cross section of a memory device 100according to one embodiment, the memory device 100 comprising memorycells 1 that may correspond to the memory cell 1 of Fig. 2a. The shownmemory device has a bottom electrode 5 that is shared between memory cells 1 and a plurality of top electrodes 9, each of which also may be shared between memory cells 1, although not shown in the cross section view of Fig.2b. The memory device may also have a pluraiity of parallei bottomelectrodes 5, although this neither is shown in the cross section view of Fig.2b. Between the electrodes 5, 9 there is arranged a ferroelectric memorylayer 7, typically a ferroelectric organic, such as polymeric, memory material,preferably as a global layer, that is, a layer shared between typically allmemory cells 1 of the memory device 100. The memory device 100 mayhave electrodes 5, 9 and a memory layer 7 correspondingly arranged asshown in Figs. 1b-d.

The stack 4 of layers in a memory cell 1, e.g. as shown in Figs. 2a-b,further comprises a protective layer 11. The protective layer 11 is adapted toprotect the electrically active part 4a from environmental and/or physicaldamage, such as scratches and abrasion. To accomplish this, the protectivelayertypically needs to have a hard outer surface, e.g. by being of a materialthat is hard, typically significantly harder than other materials in the stack 4.The protective layer 11 may be hardened, such as by curing, after depositionin a fluid state. The protection layer 11 may be a UV curable varnish that iscured by means of UV radiation. The hardening process may cause theprotective layer 11 to laterally shrink and the shrinkage may be in the range ofone or a few percent. The protective layer 11 is preferably provided as aglobal layer. The protective layer 11 typically has a thickness in a range of 2pm to 20 pm. Between the top electrode layer 9 and the protective layer 11there is arranged a buffer layer 13. The buffer layer 13 is configured to absorblateral dimensional change that may occur in the protective layer 11, e.g.such caused by shrinkage from curing of the protective layer or bytemperature Variations.

Fig. 2c schematically illustrates deformation in a buffer layer of thememory cell 1 according to the embodiment in Fig. 2a. As illustrated, a topportion 13a of the buffer layer 13 is attached to the protective layer 11 and abottom portion 13b of the buffer layer 13 is attached to the top electrode layer9. Curing of the protective layer 11 may result in a lateral dimensional changeAL of a protective layer portion which before the dimensional change was covering the lateral area of the memory cell 1. When there is a lateral 16 dimensional change lateral dimensional change AL in the protective layer, thetop portion 13a of the buffer layer 13 may deform correspondingly as shownin Fig. 2c. However, owing to softness of the buffer Iayer 13, the bottomportion 13b of the buffer layer 13, that is, where the buffer layer is attached tothe top electrode layer 9, may be virtually unaffected by the Iateraldimensional change AL of the protective layer.

The buffer layer 13 thereby absorbs the Iateral dimensional change ALsuch that it substantialiy does not reach and affect the top electrode layer 9,or only to a reduced extent. The buffer layer 13 has a thickness or height H.The ability of the buffer layer 13 to absorb Iateral dimensional changes maydepend on the thickness H of the buffer layer 13 and material properties.Although very thick buffer layers may be at least theoretically possible to use,it is often desirable or required, e.g. of manufacturing or application reasons,not to use too thick buffer layers. The buffer layer 13 typically has a thicknessH in a range of 2 to 20 pm. A buffer layer 13 having desired properties maybe accomplished by letting the buffer layer comprise, or consist, of a materialthat has a glass transition temperature Tg below room temperature, i.e. belowabout 25 degrees C or below about 30 degrees C, and preferably aboveabout -130 degrees C or above about -90 degrees C.

Such range defines a large number of polymeric materials that havesuitable material properties. A polymer material with such Tg has an elasticitythat enables absorption of a Iateral dimension change AL as described inconnection with Fig 2c. One specific example of such suitable polymer ispolypropylene glycol (PPG), which is also printable. Other examples includesilicon rubber, natural rubber, polyvinyl acetate and acrylate based resins.

A buffer layer material with Tg in the described ranges may furtherprovide ability to absorb deformation in a “through layer” direction, that is,perpendicular to the Iateral direction. Vertical dimensional changes orirregularities in the top electrode layer 9 can thereby be absorbed by thebuffer layer 13.

Fig. 3 schematically shows a cross section of a memory cell 1according to another embodiment having reduced risk of shorts to occur.Corresponding to the previously discussed memory cell embodiments, the 17 memory cell 1, marked out by dashed lines, also here comprises a stack oflayers arranged on a flexible substrate 3. The electrically active part 4a of thememory cell 1, that is, layers 5,7,9 may be in accordance what has beendiscussed above. There is also a here a protective layer 11 for protecting theelectrically active part against scratches and abrasion. The protective layer issuspended above the top electrode layer 9 by spacers 14 arranged on thesubstrate 3 on opposite sides of the electrically active part 4a. ln a gapprovided by the suspension there is confined a non-coherent material forminga buffer layer 13. The non-coherent material may preferably be a gas, forexample carbon dioxide. The buffer layer 13 may in this embodiment thuscorrespond to a gas filled gap, such as a gap filled with carbon dioxide or anair-gap. Also other non-coherent material, which typically are such havingvery low glass transition temperatures Tg, may be used, not only materialsthat are in gas phase at room temperature. Non-coherent materials may haveglass transition temperatures that are significantly lower than Tg of thematerials discussed in connection with the previously discussed embodiment,which involved coherent buffer layer materials. The spacers 14 may be stripsof tape, e.g. arranged parallel to electrodes of a memory device of array ormatrix type, or strips that are printed. ln other embodiments the spacers 14may be printed dots. ln alternative embodiments the spacers may bearranged not directly on the substrate 3, but on any one of other layers 5,7,9of the memory cell 1, which extends outside the area of the memory cell 1, forexample on a globally provided ferroelectric memory material layer 7 in amemory device 100 of array or matrix type. The non-coherent material maybe kept in place laterally by e.g. spacers arranged outside the memory cellarea of a memory device 100, which spacers may circumvent the memory cellarea and provide sealing between e.g. the substrate 3 and the protectivelayer 11 which is sufficiently tight for keeping the non-coherent material inplace. The protective layer is preferably in the form of a protective hard film inthis embodiment, which e.g. may be attached by glue or by clamping.Examples of such protective film includes e.g. protective films that arecommonly used to protect touch screens of smart phones, kapton tape, and similar. 18 Another solution that has been found to the problem of reducing therisk of shorts to occur, and which may be used in combination with the bufferlayer discussed above, is to initiaiize (electrically switch) the memory cellsbefore the protection layer is provided, or at least before it is hardened afterdeposition. Experiments have clearly demonstrated that such initializationmay decrease the risk of shorts to occur.

Fig. 4 is a flow chart illustrating a method for producing a memory cell1 comprising a stack 4 of layers arranged on a flexible substrate 3, which maya memory cell as discussed in the foregoing. ln a step 110 there is provided asubstrate 3 and arranged thereon an electrically active part 4 of said stack,the electrically active part 4a comprising a bottom electrode layer 5 and a topelectrode layer 9 separated by at least one ferroelectric memory materiallayer 7. The electrically active part may be printed, for example as disclosedin WO2006/135246. ln a step 140 a protective layer 11 for protecting theelectrically active part against scratches and abrasion is provided. Theelectrically active part 4a may in a step 120 be electrically operated beforeproviding the protective layer 11. Electrically operating the electrically activepart here involves switching polarity in the ferroelectric memory material layer7 which involves applying voltages of opposite polarity and of magnitudesgreater than a coercive voltage of the ferroelectric memory material. Thenumber of switch cycles may be in the order of 100, e.g. 300. Providing theprotective layer 11 may involve depositing a layer in a fluid form andsubsequently hardening the deposited layer, such as by curing. lf providingthe protective layer 11 involves subsequent hardening, the step 120 ofelectrically operating may be performed after deposition but before thehardening. ln a step 130 a buffer layer 13 may be provided on top of saidelectrically active part 4b of said stack before providing the protective layer11, wherein the buffer layer 13 may be a buffer layer as discussed in theforegoing. Step 120 and 130 are both being performed in some embodiments,while in other embodiments step 120 may be performed but not step 130, andin yet other embodiments, step 130 is performed but not step 120. ln oneembodiment the method involves printing of the electrically active part. Themethod may also involve printing of the buffer layer. 19 ln a detailed example, a memory device comprising memory cellsaccording to one embodiment, is produced according to the following: A 50um thick substrate 3 is made of PET (e.g. Toray XG532), on top of which a100 nm thick (patterned) bottom electrode layer 5 of Ag (e.g. lnktec TEC-RA2) is gravure printed. A 150 nm thick ferroelectric memory material layer 7of P(VDF/TrFE) is micro gravure coated (as a global layer) on the bottomelectrode layer and then a 100 nm thick (patterned) top electrode layer 9 ofAg (e.g. lnktec TEC-RA2) is gravure printed thereon. On the top electrodelayer a 10 um thick buffer layer 13 of (silane-terminated) PPG is screenprinted (as a global layer). The stack 4 of layers on the substrate 3 is thenterminated by a 5 pm thick protective-layer 11 of UV curable varnish (SunChemical UV6630) is screen printed (as a global layer) and subsequentlycured. The lateral area of each memory cell of the memory device is about200 um x 200 um.

As understood by the skilled person, the problem and solutionpresented herein may be relevant also in case of other electric devices orcomponents than the kind of memory devices and memory cells discussedabove, generally for any electronic device or component comprising a stack oflayers arranged on a flexible substrate, wherein an electrically active part thestack comprises a bottom electrode layer and a top electrode layer separatedby at least one insulating or semi-insulating layer and where the stack isterminated by a protective layer for protecting the electrically active partagainst detrimental external influence, such as physical damage throughscratches or abrasion, moisture etc. Non-limiting examples of such otherelectric devices or components involve: - Transistors, in particular thin film transistors (TFTs), and moreparticularly printable TFTs, where the source and/or drain may correspond tothe bottom electrode, the gate to the top electrode and there is an insulatinglayer separating the gate from the source and drain. ln a transistor shortsdesirable to reduce may occur between the source or drain and the gate, and/or between the source and drain.

- Photo voltaic cells, based on organic and/or inorganic materials, orphoto cells, which also have a capacitor like structure with top and bottomelectrodes separated by at least one insulating or semi-insulating layer.

- Other kind of memory devices or cells, based on other memorymaterial and/or technology. Such memory devices may require active insteadof passive arrangement of the memory cells.

Any illustration and description in the drawings and in the foregoingdescription are to be considered exemplary and not restrictive. The inventionis not limited to the disclosed embodiments.

For example, there may be embodiments with one or moreintermediate or interface layers between any of the layers in described stackand/or substrate. For example, there may be one or more functionalintermediate layers between the electrodes and the memory material, e.g. inorder to promote adhesion or reduce detrimental phenomena related to thememory material used and/or the passive matrix addressing.

The present invention is defined by the claims and variations to thedisclosed embodiments can be understood and effected by the person skilledin the art in practicing the claimed invention, for example by studying thedrawings, the disclosure, and the claims. Use of the word "comprising" in theclaims does not exclude other elements or steps, and use of the article "a" or"an" does not exclude a plurality. Occurrence of features in differentdependent claims does not per se exclude a combination of these features.Any method claim is not to be construed as limited merely because of thepresentational order of the steps. Any possible combination betweenindependent steps of any method claim shall be construed as being withinscope, although the independent steps, by necessity must, occur in someorder. Any reference signs in the claims are for increased intelligibility and shall not be construed as limiting the scope of the claims.

Claims (27)

1. An electronic component (1) comprising a stack (4) of layers arrangedon a flexible substrate (3), wherein said stack comprises an electrically activepart (4a) and a protective layer (11) for protecting the electrically active partagainst scratches and abrasion, wherein said electrically active partcomprises a bottom electrode layer (5) and a top electrode layer (9) and atleast one insulating or semi-insulating layer (7) between said electrodes,wherein the stack further comprises a buffer layer (13), arranged between thetop electrode layer (9) and the protective layer (11), the buffer layer (13) beingadapted for at least partially absorbing a lateral dimensional change (AL)occurring in the protective layer (11) and thus preventing said dimensionalchange (AL) from being transferred to the electrically active part (4a).

2. The electronic component as claimed in claim 1, wherein at leastpartially absorbing the lateral dimensional change comprises absorbing thelateral dimensional change by at least 99%, or by at least 95%, or by at least90%, or by at least 80%, or by at least 50%, or by at least 30%.

3. The electronic component as claimed in any one of claims 1-2, whereinthe buffer layer (13) is adapted for at least partially absorbing the lateraldimensional change (AL) by being of a coherent material and having suchlayer thickness (H) that a lateral dimensional deformation in a top portion(13a) of the buffer layer (13) facing the protective layer (11) results insubstantially less lateral dimensional deformation in a bottom portion (13b)facing the electrically active part (4a), when said lateral dimensionaldeformation in the upper part (13a) is caused by the lateral dimensionalchange (AL) of the protective layer, the difference in lateral deformationbetween the top and bottom portions corresponding to absorbed lateral dimensional change. 22

4. The electronic component as claimed in claims 3, wherein the lateraldimensional deformation in the upper part is a substantially completely elastic deformation.

5. The electronic component as claimed in any one of claims 1-4, whereinthe buffer layer comprises a material with a glass transition temperature Tgthat is lower than 30 degrees C or preferably lower than 25 degrees C.

6. The electronic component as claimed in claim 5, wherein the materialis a hybrid material comprising at least one material component that has aglass transition temperature Tg that is lower than 30 degrees C or preferably lower than 25 degrees C.

7. The electronic component as claimed in claim 6, wherein the at leastone material component constitutes at least 50% of the hybrid material, atleast 80%, or at least 90% of the hybrid material.

8. The electronic component as claimed in any one of claims 5-7, whereinthe buffer layer comprises a material with a glass transition temperature Tgthat is higher than -130 degrees C or preferably higher than -90 degrees C.

9. The electronic component (1) as claimed in any one of claims 1-8,wherein the buffer layer (13) comprises a material or mix of two or morematerials from any one of the following: silicon rubber, natural rubber, polypropylene glycol, polyvinyl acetate and acrylate based resins.

10. The electronic component as claimed in any one of claims 1-9, wherein the buffer layer (13) has a thickness in a range of 1-40 um.

11. The electronic component (1) as claimed in any one of claims 1-10,wherein the electronic component (1) comprises a ferroelectric memory cell and the insulating or semi-insulating layer is a layer of ferroelectric memory 23 material, preferably an organic, such as a polymeric, ferroelectric memory material.

12. The electronic component as claimed in any one of claims 1-11,wherein said Iateral dimensionai change (AL) of the protective layer (11) issuch causable by hardening of the protective layer, such as by curing, or bytemperature differences in an operational temperature range of the electronic component, such as -10C to +50C.

13. The electronic component as claimed in any one of claims 1-12,wherein said Iateral dimensionai change (AL ) of the protective layer (11) isabout or below 3%, preferably about or below 2%, more preferably about or below 1%, in any Iateral direction.

14. The electronic component as claimed in any one of claims 1-13,wherein the electrically active part (4a) and/or the buffer layer (13) has beenprinted on the flexible substrate.

15. The electronic component as claimed in any one of claims 1-14,wherein the protective layer is directly attached to the buffer layer.

16. The electronic component as claimed in any one of claims 1-15,wherein the protective layer (11) comprises a material that has beenhardened, such as by means of curing, after it has been deposited on thestack (4).

17. The electronic component (1) as claimed in claim 16, wherein theprotective layer (11) comprises a protective film (11a) and an adhesive (11b)attaching the protective film to the buffer layer (13), the material that has been hardened being the adhesive.

18. The electronic component (1) as claimed in any one of claims 1-16,wherein the protective layer (11) is a protective film and the buffer layer (13) 24 forms an adhesive attaching the protective film (11) to the rest of the stack (4)-

19. The electronic component (1) as claimed in claim 1, wherein the bufferlayer (13) is formed of a non-coherent material confined between the protective layer (11) and the top electrode layer (9).

20. The electronic component (1) as claimed in claim 19, wherein the non-coherent material is as gas, the buffer layer (13) preferably corresponding toa gas filled gap, such as a gap filled with carbon dioxide or an air-gap.

21. Use of a buffer layer (13) for reduction of short circuits in an electroniccomponent (1), the buffer layer being arranged between a top electrode layer(9) and a protective layer (11) in the electronic component (1), the electroniccomponent (1) comprising a stack (4) of layers arranged on a flexiblesubstrate (3), wherein said stack comprises an electrically active part (4a) anda protective hard layer (11) for protecting the electrically active part againstscratches and abrasion, wherein said electrically active part comprises abottom electrode layer (5) and a top electrode layer (9) and at least oneinsulating or semi-insulating layer (7) between said electrodes.

22. Use of a material with a glass transition temperature (Tg) that is lowerthan 30 degrees C or preferably lower than 25 degrees C for forming a bufferlayer (13) for reduction of short circuits in an electronic component (1), thebuffer layer being arranged between a top electrode layer (9) and a protectivelayer (11) in the electronic component (1), the electronic component (1)comprising a stack (4) of layers arranged on a flexible substrate (3), whereinsaid stack comprises an electrically active part (4a) and a protective hardlayer (11) for protecting the electrically active part against scratches andabrasion, wherein said electrically active part comprises a bottom electrodelayer (5) and a top electrode layer (9) and at least one insulating or semi-insulating layer (7) between said electrodes.

23. A method for producing an electronic component (1) comprising astack (4) of Iayers arranged on a flexible substrate (3), said methodcomprising: - providing (110) said substrate (3) and arranged thereon an electricallyactive part (4) of said stack, the electrically active part (4a) comprising abottom electrode layer (5) and a top electrode Iayer (9) separated by at leastone insulating or semi-insulating layer (7); - providing (140) a protective layer (11) for protecting the electricallyactive part against scratches and abrasion; and wherein the method furthercomprises one or both of the following steps: - providing (130) a buffer layer (13) on top of said electrically activepart (4b) of said stack before providing the protective layer (11), the bufferlayer (13) being adapted for at least partially absorbing a lateral dimensionalchange (AL) occurring in the protective layer (11) and thus preventing saiddimensional change (AL) from being transferred to the electrically active part(4a); and/or - electrically operating (120) the electrically active part (4b) before providing the protective layer (11).

24. The method as claimed in claim 23, wherein providing the protectivelayer (11) involves depositing a layer in a fluid form and subsequently hardening the deposited layer, such as by curing.

25. The method as claimed in any one of claims 23-24, further comprising providing the electrically active part (4a) by printing.

26. The method as claimed in any one of claims 23-25, further comprising providing the buffer layer (13) by printing.

27. An electronic device (100) comprising one or more electronic components (1) as claimed in any one of claims 1-20.