SE0004913D0 - Processor - Google Patents
ProcessorInfo
- Publication number
- SE0004913D0 SE0004913D0 SE0004913A SE0004913A SE0004913D0 SE 0004913 D0 SE0004913 D0 SE 0004913D0 SE 0004913 A SE0004913 A SE 0004913A SE 0004913 A SE0004913 A SE 0004913A SE 0004913 D0 SE0004913 D0 SE 0004913D0
- Authority
- SE
- Sweden
- Prior art keywords
- processor
- value
- speculated
- speculation
- failed
- Prior art date
Links
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Retry When Errors Occur (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE0004913A SE0004913D0 (sv) | 2000-12-29 | 2000-12-29 | Processor |
PCT/SE2001/002912 WO2002054229A1 (en) | 2000-12-29 | 2001-12-27 | Processor architecture for speculated values |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE0004913A SE0004913D0 (sv) | 2000-12-29 | 2000-12-29 | Processor |
Publications (1)
Publication Number | Publication Date |
---|---|
SE0004913D0 true SE0004913D0 (sv) | 2000-12-29 |
Family
ID=20282488
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE0004913A SE0004913D0 (sv) | 2000-12-29 | 2000-12-29 | Processor |
Country Status (2)
Country | Link |
---|---|
SE (1) | SE0004913D0 (sv) |
WO (1) | WO2002054229A1 (sv) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20230126908A1 (en) * | 2021-10-27 | 2023-04-27 | International Business Machines Corporation | Protection against executing injected malicious code |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5966544A (en) * | 1996-11-13 | 1999-10-12 | Intel Corporation | Data speculatable processor having reply architecture |
US5781752A (en) * | 1996-12-26 | 1998-07-14 | Wisconsin Alumni Research Foundation | Table based data speculation circuit for parallel processing computer |
US6205542B1 (en) * | 1997-12-24 | 2001-03-20 | Intel Corporation | Processor pipeline including replay |
-
2000
- 2000-12-29 SE SE0004913A patent/SE0004913D0/sv unknown
-
2001
- 2001-12-27 WO PCT/SE2001/002912 patent/WO2002054229A1/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
WO2002054229A1 (en) | 2002-07-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE69916962D1 (de) | Datenverarbeitungssystem mit bedingter Ausführung von erweiterten Verbundbefehlen | |
WO2002041146A3 (en) | Instruction processor systems and methods | |
IL171906A (en) | Instructions to assist the processing of a cipher message | |
DE60044300D1 (de) | Daten-prozessor | |
KR910012910A (ko) | 저소비 전력 반도체 집적회로장치 및 마이크로 프로세서 | |
GB2377795A (en) | Isolated instructions for isolated execution | |
GB2427492A (en) | Method and apparatus for dynamically adjusting the aggressiveness of an execute-ahead processor | |
FR2787900B1 (fr) | Circuit integre intelligent | |
WO2007021704A3 (en) | Application acceleration using heterogeneous processors | |
MY134441A (en) | System for invoking a privilieged function in a device | |
WO2002086699A3 (en) | Microprocessor for executing byte compiled java code | |
TW200500944A (en) | Apparatus and method for managing a processor pipeline in response to exceptions | |
EP1372064A3 (en) | Processor and program conversion method | |
WO2005048010A3 (en) | Method and system for minimizing thread switching overheads and memory usage in multithreaded processing using floating threads | |
WO2004086220A3 (de) | Kontrollierte ausführung eines für eine virtuelle maschine vorgesehenen programms auf einem tragbaren datenträger | |
US20040168047A1 (en) | Processor and compiler for creating program for the processor | |
WO2005038646A3 (en) | Selectively deferring the execution of instructions with unresolved data dependencies | |
WO2006001946A3 (en) | Method for improved reissue of deferred instructions | |
MX2008000623A (es) | Sistema y metodo para controlar multiples hilos de ejecucion de programa dentro de un procesador de hilos de ejecucion multiples. | |
ATE542577T1 (de) | Ansteuerung von mehreren vorrichtungen | |
DE60239832D1 (de) | Benutzerprioritätsmodus | |
SE0004913D0 (sv) | Processor | |
JP2004280801A (ja) | プロセッサおよびこのプロセッサ用のプログラムを生成するコンパイラ装置 | |
JP2007334497A (ja) | 情報処理装置の省電力化方法、プログラム、およびプログラム実行システム | |
DE60217104D1 (de) | Erweiterbares befehlssystem |