RU94785U1 - NETWORK TRAFFIC ANALYSIS DEVICE - Google Patents

Abstract

 Network traffic analysis device containing (i = 1 ... N) thinning logic circuits, (i = 1 ... N) elements And, (i = 1 ... N-1) counters, (i = 1 ... N-1) multipliers, counter D, divider, adder, multiplier, trigger block, the output of which is connected to the inputs of thinning logic circuits (i = 1, 2, ..., N), the output “pass” of the first thinning logic circuit is connected to the first and second inputs of the first AND element, except Moreover, the output “transmission” (i = 2 ... N) of the throttling logic circuit is connected to the second input (i = 2 ... N) of the And element, the output of each i-th And element, except by the Nth one is connected to the first inputs of the subsequent element And, accordingly, the input of the start block is the information input of the device, the output of the divider is connected to the second input of the multiplier, the output of the adder is connected to the first input of the multiplier, characterized in that the Nth counter is additionally introduced into it, Nth multiplier, timer, memory block, Δk calculation block, calculation block, calculation block, difference block, 1 / S (n) calculation block, multiplier, logarithm block, Hurst coefficient value estimation block, and the timer output is connected to the block input behind start, outputs (i = 1 ... N) of the logic circuit AND are connected to the inputs of the (i = 1 ... N) of the counter, outputs "pass" of each i-th thinning logic circuit are connected to the first inputs of each i-th multiplier and the inputs of the memory unit, the output of which is connected to the first input of the calculation unit 1 / S (n) and the first input of the calculation unit Δk, the outputs of the counters are connected to the second input of the multipliers, the outputs of the multipliers are connected to the inputs of the adder, the output of the multiplier is connected to the second input of the calculation unit 1 / S (n) and with the second input of the calculation unit Δk, the output of the calculation unit Δk is connected to

Description

The utility model relates to computer technology and is designed to determine the fractal properties of network traffic and identify network protocols; it can be used in switching nodes of messages, packets, and cells of a data transmission network.

A known method and device for measuring traffic in a communication system - see the invention "Method and device for measuring traffic in a communication system", A.S. No. 955406, H04L 12/5, 11/08/96. In the specified invention, the operation of the device consists in receiving a sequence of traffic units, filtering it by thinning logic circuits in accordance with the established decimation parameters, generating a resolution signal by the i-th “And” circuit for i + 1 “And” circuits, comparing the signals coming from neighboring circuits “AND” in the “EXCLUSIVE OR” elements, counting of single impulses coming from the output of the “EXCLUSIVE OR” elements.

The disadvantage of this analogue is that when measuring traffic, a priori data on the behavior of the external source from which the traffic is received are not taken into account, traffic data may be belated in nature and not reflect the current state.

The closest in its technical essence and functions to the prototype of the claimed device is the invention "Method and device for predicting traffic in a communication system" - patent No. 2258316, H04L 12/56, 08/10/2005, which solves the problem of predicting network traffic.

The known device contains a traffic filtering unit, consisting of (i = 1 ... N) thinning logic circuits (G), (i = 1 ... N) elements "And", (i = 1 ... N-1) elements "Exclusive OR", (i = 1 ... N-1) counters, a start-up block, the output of which is connected to the inputs of thinning logic circuits (i = 1, 2 ... N), the output "pass" of the first thinning logic circuit is connected to the first and second inputs of the first element "AND ", in addition, the output" transmission "(i = 2 ... N) of the thinning logic is connected to the second input (i = 2 ... N) of the" And "element, the output of each i-th element" And ", for excluded the Nth element is connected to the first inputs of the subsequent And element, respectively, the outputs of each (i = 1 ... N-1) th And element are connected to the first input of the (i = 1 ... N-1) of the Element Exclusive OR "respectively, in addition, the outputs of the (i = 2 ... N) th element" AND "are connected to the second inputs of the (i = 1 ... N-1) th element" Exclusive OR "respectively, the outputs of the i-th element" The exclusive OR "are the input of the i-th counter, the input of the start-up block is the information input of the devices, and also contains difference blocks B (i = 1 ... N-1), multipliers X (i = 1 ... N-1), counter D, divider K, adder S, multiply T, and the output of the trigger unit is connected to the input of the counter D, the output of which is connected to the input of the divider K, the output of which is connected to the second input of the multiplier T, the second output of each i-th thinning logic circuit except the N-th one is connected to the first inputs i = 1 ... N-1 elements of blocks of difference B, respectively, the second outputs of the 2 ... N-th thinning logic circuit are connected to the second inputs i = 1 ... N-1 of the blocks of difference B, respectively, the outputs of the blocks of difference B are connected to the first inputs of the multipliers X, by the second input of which the outputs are connected counter s (i = 1 ... N-1), the outputs of the multipliers X (i = 1 ... N-1) are connected to the inputs (i = 1 ... N-1) of the adder S, the output of which is connected to the first input of the multiplier T, and the information input traffic filtering unit is the start-up unit to which the communication channel is connected, the first information output is the output of the multiplier T, and the second is the output of the counter D. The known device also contains an autocorrelation function calculation unit, an autoregression parameter calculation unit, an autoregression filter unit, and the communication channel connected to the information input of the fil block traffic flow, the first information input of the autocorrelation function calculation unit and the second information input of the autoregressive filter unit, and the output of the filtering unit is connected to the second input of the autocorrelation function calculation unit, the information output of the autocorrelation function calculation unit is connected to the information input of the autoregression parameter calculation unit, and the information output of the unit calculating autoregressive parameters is connected to the second information input of the autoregressive filter unit, the output of which is I exit the system.

The essence of the known invention consists in the reception by the traffic filtering unit of a sequence of traffic units, its filtering by decimating logic circuits in accordance with the established decimation parameters, determining an estimate of the distribution of traffic units by occurrence frequency by simultaneously computing estimates of the occurrence frequency in several ranges of values. Next, the mathematical expectation of the arrival time of traffic units is estimated by simultaneously subtracting the values of the traffic units of neighboring ranges, followed by multiplying the results by the relative frequencies of occurrence of the corresponding distributions of traffic units. Then, in the block for calculating the autocorrelation function, based on the result obtained, the autocorrelation function of the random process characterizing the time of arrival of traffic units is calculated. In the block of calculating the autoregression parameters, the filter weighting coefficients are calculated, based on which the arrival time κ + 1, 2, ..., n traffic units are predicted in the autoregression filter block. Thus, the prediction of the values of the frequency of arrival of traffic units or the time between the arrival of its individual units.

The disadvantage of this device is the inability to assess with its help the fractal properties of network traffic and the identification of network protocols. The disadvantage is due to the fact that bursts of traffic are smoothed out in the device due to the implementation of an averaging effect in it. To implement the assessment of the fractal properties of network traffic, there is no need to calculate the autocorrelation function of a random process.

The task to which the claimed utility model is directed is to create a network traffic analysis device that allows identifying network protocols based on an assessment of fractal properties.

This task is achieved by the fact that the network traffic analysis device containing (i = 1 ... N) thinning logic circuits, (i = 1 ... N) elements "And", (i = 1 ... N-1) counters, (i = 1 ... N-1) multipliers, counter D, divider, adder, multiplier, trigger unit, the output of which is connected to the inputs of thinning logic circuits (i = 1, 2, ..., N), the output “pass” of the first thinning logic circuit is connected to the first and the second inputs of the first “And” element, in addition, the output “transmission” (i = 2 ... N) of the thinning logic circuit is connected to the second input (i = 2 ... N) of the “And” element, you the course of each i-th element "And", except for the N-th one, is connected to the first inputs of the subsequent element "And", respectively, the input of the start-up block is the information input of the device, the output of the divider is connected to the second input of the multiplier, the output of the adder is connected to the first input of the multiplier, additionally introduced the Nth counter, Nth multiplier, timer, memory unit, calculation unit Δ _k , calculation unit calculation block , 1 / S (n) calculation block, difference block, multiplier, logarithm block, Hurst coefficient value estimator, and the timer output is connected to the input of the start block, the outputs (i = 1 ... N) of the AND logic circuit are connected to the inputs of the (i = 1 ... N) -th counter, the outputs “transmission” of each i-th thinning logic circuit are connected to the first inputs of each i-th multiplier and the inputs of the memory block, the output of which is connected to the first input of the 1 / S calculation block (n ) and with the first input of the calculation unit Δ _k , the outputs of the counters and the outputs of the multiplier are connected to the second input of the multipliers th are connected to the inputs of the adder, the output of the multiplier is connected to the second input of the calculation unit 1 / S (n) and to the second input of the calculation unit Δ _k , the output of the calculation unit Δ _{k is} connected to the input of the calculation unit and with the input of the calculation unit calculation block output connected to the first input of the difference block, the output of the calculation block connected to the second input of the difference block, the output of which is connected to the second input of the multiplier, to the first input of which the output of the calculation unit 1 / S (n) is connected, the output of the multiplier is connected to the input of the logarithm unit, the output of which is connected to the input of the block for estimating the value of the Hurst coefficient, output unit estimates the value of the Hurst coefficient is the information output of this device, which receives the value of the estimation of the Hurst coefficient.

Thanks to a new set of essential features, due to the introduction of new elements and the relationships between them, the device allows you to evaluate the fractal properties of network traffic by the value of the Hurst coefficient and by this value identify network protocols.

The analysis of the prior art by the applicant made it possible to establish that there are no analogs characterized by sets of features identical to all the features of the device claimed in the utility model for determining the fractal properties of network traffic. Therefore, the utility model meets the condition of patentability “novelty”.

The claimed utility model is illustrated in the drawing (Figure 1), which shows a functional diagram of a network traffic analysis device.

The claimed network traffic analysis device shown in FIG. 1 contains: a start block 1, a timer 2, a first decimation logic 3.1, a second decimation logic 3.2, an Nth decimation logic 3.N, a first element “AND” 4.1, a second “And” element 4.2, Nth element “And” 4.N, first counter 5.1, second counter 5.2, Nth counter 5.N, counter D 6, first multiplier 7.1, second multiplier 7.2, Nth multiplier 7 .N, memory block 8, divider 9, adder 10, multiplier 11, calculation unit 1 / S (n) 12, calculation unit Δ _k 13, calculation unit 14, calculation unit 15, difference block 16, multiplier 17, logarithm block 18, Hurst coefficient value estimator 19. The input of the start block 1 is the information input of the device and is connected to the counter D 6, the output of the timer 2 is connected to the input of the start block 1, the output of the start block 1 is connected to the inputs of thinning logic circuits 3.1-3.N, the output of thinning logic circuit 3.1 is connected to the first and second inputs of the element "And" 4.1, to the input of the memory unit 8 and to the first input of the multiplier 7.1, the outputs of thinning logic circuits 3.2-3.N are connected with second element inputs "And" 4.2-4.N and the first inputs of the multipliers 7.2-7.N, respectively, and the inputs of the memory unit 8, the outputs of the elements "And" 4.1-4.N-1 are connected to the first inputs of the elements "And" 4.2-4.N and with the inputs of the counters 5.1-5.N-1, respectively, the output of the circuit “AND” 4.N is connected to the input of the counter 5.N, the outputs of the counters 5.1-5.N are connected to the second inputs of the multipliers 7.1-7.N, respectively, the outputs of the multipliers 7.1 -7.N are connected to the inputs of the adder 10, the output of the counter D 6 is connected to the input of the divider 9, the output of the divider 9 is connected to the second input of the multiplier 11, the output of the adder 10 is connected to the first input of the multiplier I 11, the output of the multiplier 11 is connected to the second input of the calculation unit 1 / S (n) 12 and to the second input of the calculation unit Δ _k 13, the output of the memory unit 8 is connected to the first input of the calculation unit 1 / S (n) 12 and to the first input calculation unit Δ _k 13, the output of the calculation unit Δ _k 13 is connected to the input of the calculation unit 14 and with the input of the calculation unit 15, the output of the calculation unit 14 is connected to the first input of the difference block 16, the output of the calculation unit 15 is connected to the second input of the difference block 16, the output of the difference block 16 is connected to the second input of the multiplier 17, the output of the calculation unit 1 / S (n) 12 is connected to the first input of the multiplier 17, the output of the multiplier 17 is connected to the input of the logarithm unit 18, the output of the logarithm unit 18 is connected to the input of the Hurst coefficient value estimator 19, the output of the Hurst coefficient value estimator 19 is the output of the device.

Launcher 1 is designed to receive an output pulse for each incoming traffic unit; it is known and described, for example, in the book by Mandle M. 200 selected electronics circuits: Per. from English 2nd ed., Stereotype., - M .: Mir, 1985. - p. 350, ill. in clause 8.2.

Timer 2 sets the time of observation, it is known and described, for example, in the reference book Integrated circuits and their foreign analogues: Reference. Volume 7. / A.V. Nefedov. - M .: IP RadioSoft, 1999 - 640 p .: ill. and can be implemented on the chip KR1006VI1.

The work of a separate thinning circuit in the proposed matrix of thinning logic circuits 3.1-3.N can be carried out on the basis of the principle of "leaking bucket", known from the prior art. A description of the operation of the decimation circuit is given in patent No. 22258316, class H04L 12/56, 04.25.2003. The principle of a “leaking bucket” is disclosed, for example, in: (Ralf O. Onvural: Asynchronous Transfer Mode Networks, Performance Issues, Arctech House Inc. 1994 (ISBN 0-89006-662-0), Chapter 4.5.1).

The set of logic circuits “AND” 4.1-4.N is designed to prevent the decision to “skip” the logic of a lower order, when the logic of a higher level decides to “interrupt”. Each of the logical circuits “I” is known and described, for example, in the book of Tokheim R. Fundamentals of Digital Electronics: Per. from English - M .: Mir, 1988 .-- 392 s, ill. on pages 47-50, on pages 66-70.

Counters 5.1-5.N are designed to count the number of skip decisions made by thinning logic circuits. Each of the counters can be implemented by serial connection of known counters, described, for example, in the book of Tokheim R. Fundamentals of Digital Electronics: Per. from English - M .: Mir, 1988 .-- 392 s, ill. on pages 176-177.

The counter D 6 is designed to calculate the total number of units of traffic on the observation interval, can be implemented by serial connection of well-known counters, described, for example, in the book of Tokheim R. Fundamentals of Digital Electronics: Per. from English - M .: Mir, 1988 .-- 392 s, ill. on pages 176-177.

Multipliers 7.1-7.N are designed to multiply the values of the time of arrival of traffic units by the number of these values. Each of the 7.1-7.N multipliers is known and described, for example, in the book of Tokheim R. Fundamentals of Digital Electronics: Per. from English - M .: Mir, 1988 .-- 392 s, ill. on pages 236-241.

The memory unit 8 is designed to store the frequency of occurrence of values of the time of arrival of traffic units, estimated using thinning logic 3.1-3.N in the order of their arrival, is a known device and is described, for example, in the book Figurnova V.E "IBM PC for the user" - 7th edition. - Moscow, Infra-M. - 1998 on p. 123-127.

The divider 9 performs the operation of dividing 1 by the total number of traffic units in the observation interval, that is, it calculates the value inverse to the total number of traffic units in the observation interval. Divider 9 is known and described, for example, in the book of the book by Tokheim R. Fundamentals of Digital Electronics: Per. from English - M .: Mir, 1988 .-- 392 s, ill. on pages 178-180.

The adder 10 performs the addition of the values obtained from the outputs of the multipliers 7.1-7.N, known and described, for example, in the book of Tokheim R. Fundamentals of Digital Electronics: Per. from English - M .: Mir, 1988 .-- 392 s, ill. on pages 213-216.

The multiplier 11 calculates the mathematical expectation of the arrival time of the traffic units on the observation interval by multiplying the values obtained from the output of the adder 10 and the divider 9. The multiplier 11 is known and described, for example, in Tokheim R. Fundamentals of Digital Electronics: Per. from English - M .: Mir, 1988 .-- 392 s, ill. on pages 236-241.

The calculation unit 1 / S (n) 12 is designed to calculate the value of the inverse of the standard deviation. It can be implemented on the basis of micro-computers, described, for example, in the book Kako N., Yamane Ya. Sensors and micro-computers: Per. with japan. - L .: Energoatomizdat. Leningra. Otdel, 1986. - 120 pp., ill. on pages 44-47.

Δ _k calculating unit 13 calculates the deviation values, it is known and can be implemented based on a microcomputer, described, e.g., in the book Kako N., H. Yamane sensors and microcomputers: Trans. with japan. - L .: Energoatomizdat. Leningra. Otdel, 1986. - 120 pp., ill. on pages 44-47.

Calculation block 14 is intended to obtain a maximum deviation value. It can be implemented based on a digital comparator. Comparator circuits are known and described, for example, in the book Shilo V.L. Popular digital circuits. - M .: Radio and communications, 1987. - S.270-271.

Calculation block 15 is intended to obtain a minimum deviation value. It can be implemented based on a digital comparator. Comparator circuits are known and described, for example, in the book Shilo V.L. Popular digital circuits. - M .: Radio and communications, 1987. - S.270-271.

The difference block 16 is designed to obtain a span value, that is, the difference between the maximum and minimum deviation. It can be implemented on the basis of the subtractor described in the book of Tokheim R. Fundamentals of Digital Electronics: Per. from English - M .: Mir, 1988 .-- 392 s, ill. on pages 246-248.

The multiplier 17 multiplies the span values obtained from the output of the difference block 16 and the reciprocal of the standard deviation obtained from the calculation unit 1 / S (n) 12, which is known and described, for example, in Tokheim R. Fundamentals of Digital Electronics: Per. from English - M .: Mir, 1988 .-- 392 s, ill. on pages 236-241.

The logarithm unit 18 calculates the logarithm of the mathematical expectation of the normalized range. It can be implemented on the basis of micro-computers, described, for example, in the book Kako N., Yamane Ya. Sensors and micro-computers: Per. with japan. - L .: Energoatomizdat. Leningra. Otdel, 1986. - 120 pp., ill. on pages 44-47.

The unit for estimating the value of the Hurst coefficient 19 is calculated by the least squares method described, for example, in the book of I. N. Bronshtein, K. A. Semendyaev Handbook of mathematics for engineers and students of technical schools. - M .: 1980, 976 p., Ill. on pages 924–926, the dependence of the logarithm of the expected value of the normalized range on the logarithm of the total number of traffic units in the observation interval, and then the estimate of the Hurst coefficient N is calculated. It can be implemented on the basis of microcomputers described, for example, in the book by Kako N., Yamane Ya. Sensors and microcomputers: Per. with japan. - L .: Energoatomizdat. Leningra. Otdel, 1986. - 120 pp., ill. on pages 44-47.

The inventive device operates as follows.

To obtain an estimate of the fractal properties of network traffic, a certain time interval is required for the collection of statistical data in order to verify their stationarity. To assess stationarity with a reliability of at least 95%, it is necessary that the observation interval includes 400 or more reports of the time of arrival of traffic units. In the initial state, after turning on the power, the units of incoming traffic are sent to the launch unit 1, which generates one pulse for each incoming unit of traffic. The sequence of pulses thus obtained, which is the result of measuring traffic, is fed to the inputs of all thinning logic circuits 3.1-3.N. When the power is turned on, a timer 2 starts, connected to the start block 1 and counts the operating time of the network traffic analysis device. Each thinning circuit is tuned to its own transmission frequency. Therefore, using each of the decimating schemes, it is possible to estimate the frequency of occurrence of the ith value of the time of arrival of traffic units. Thus, the matrix of thinning logic circuits forms a variational series whose values are determined by setting the transmission frequencies of individual thinning logic circuits. In the case when the amount of incoming traffic per unit time exceeds the value of the transmission frequency, the thinning logic circuit sends some of the units of traffic to the output so that the transmission rate of the outgoing traffic from the “transmission” port is no higher than the transmission frequency that the logical scheme. Further processing of the traffic units received at the “interrupt” output can be carried out in various ways, but the ego is beyond the scope of this application for a utility model.

The signals from the output "transmission" thinning logic circuits 3.1-3.N in parallel are fed to the inputs of the elements "And" 4.1-1.N. It is assumed that the cutoff frequency value for decimation logic 3.1 is higher than the cutoff frequency limit for decimation logic 3.2, which is higher than the cutoff frequency for decimation logic 3.N. The “passing through” output of the thinning logic circuit with the highest boundary value (that is, the logic circuit of the highest level) 3.1 is connected to both inputs of the first logic circuit “AND” 4.1, and this actually means that the output in question is directly connected to the comparator, that is, the one under consideration the result is accepted as such. The output "pass" thinning logic circuit 3.2 is connected to the first input of the second logic circuit "And" 4.2, the second input of which is connected to the output of the logic circuit "And" 4.1, corresponding to thinning logic circuit 3.1 of a higher order. Similarly, the output "pass" thinning logic circuit 3.N is connected to the first input of the logic circuit "AND" 4.N, the second input of which is connected to the output of the logic circuit "AND" 4.N-1 corresponding to the thinning logic circuit 3.N- 1 higher level. The outputs of lower order logic circuits “AND” produce the result “skip” only if the output of the higher level logic circuit “AND” has the result “skip”. This prevents the decision to skip the logic of the lower level when the logic of the higher level decides to interrupt. Counters 5.1-5.N connected to the outputs of the logic circuits “AND” 4.1-4.N will give a result corresponding to the number of “skip” decisions made by thinning logic circuits.

At the same time, when the power is turned on, the values of the thinning parameters from the outputs of thinning logic circuits 3.1-3.N are sent to the memory unit 8 and to the second inputs of the multipliers 7.1-7.N, while the signals from the outputs of the counters 5.1- are sent to the first inputs of the multipliers 7.1-7.N 5.N. In memory block 8, the frequencies of occurrence of the ith value of the arrival time of the traffic units estimated using decimating logic circuits 3.1-3.N in the order of their arrival are stored. In the multipliers 7.1-7.N, the calculations are carried out X _i n _i , where X _i - ie the value of the arrival time of the unit of traffic, n _i - the number X _i . The signals from the output of 7.1-7.N multipliers are fed to the input of the adder 10. In the adder, the values obtained from the outputs of the multipliers 7.1-7.N are added. The result obtained in adder 10 is fed to the first input of multiplier 11. At the same time, pulses from the information input are sent to counter D 6. The counter D 6 counts the number of unit characters "1", the total number of which n will be equal to the number of traffic units received in the observation interval. After the arrival of each unit impulse in the observation interval, the counter value increases by one. The signal from the output of the counter D 6 goes to the input of the divider 9. In the divider, the operation of dividing by the number n is performed, that is, the calculation is performed: 1 / n. From the output of the divider 9, the signal is supplied to the second input of the multiplier 11. In the multiplier 11, the final calculation of the mathematical expectation of the time of arrival of traffic units on the observation interval is performed. Here:

1 / n is the signal received from the output of the divider 9;

- signal from the output of the adder 10.

Received expectation value output from the multiplier 11 is supplied to a first input of the calculation unit Δ _k 13 and a second input unit for calculating 1 / S (n) 12. The second input of the calculation unit Δ _k 13 and a first input of the calculation unit 1 / S (n ) 12, the values of the frequencies of occurrence of the ith value of the arrival time of the traffic units stored in the memory unit 8 in the order of their arrival are received. In the block calculation Δ _k 13 the calculation of the deviation Δ _k according to the formula:

,

Where

Δ _k is the deviation;

Where

n is the sample size;

m is the number X _i for which the calculation is made , m≤n.

In the calculation unit 1 / S (n) 12, the value of the inverse of the standard deviation 1 / S (n) is calculated by the formula:

,

Where

S (n) is the standard deviation.

The values of Δ _k from the output of the calculation unit Δ _k 13 enter the input of the calculation unit 14 and the input of the calculation unit 15, where the maximum deviation Δ _k and the minimum deviation Δ _k, respectively, are calculated. The signal from the output of the calculation unit 14 is fed to the first input of the difference block 16, the signal from the output of the calculation block 15 is fed to the second input of the difference block 16. From the output of the difference block 16, the signal arrives at the second input of the multiplier 17. The first input of the multiplier 17 receives a signal 1 / S (n) from the output of the calculation unit 1 / S (n) 12. In the multiplier 17 is multiplication and 1 / S (n). The output signal of the multiplier 17, expressed by the formula:

,

Where

R (n) - span value: ;

- the value of the normalized range.

goes to the input of the logarithm unit 18. In the block logarithm 18 calculates the logarithm of the expected value of the normalized range . The value of the logarithm of the expected value of the normalized range from the output of the logarithm unit 18 is input to the unit for estimating the value of the Hurst coefficient 19. In the unit for estimating the value of the Hurst coefficient 19 using the least square method, the dependence from log (n), and then the estimate of the Hurst coefficient N is calculated. Based on the obtained value of the Hurst coefficient H, the network protocol can be further identified.

Thus, with such a combination of essential features, the identification of network protocols is ensured by obtaining an estimate of the Hurst coefficient.

Claims (1)

Network traffic analysis device containing (i = 1 ... N) thinning logic circuits, (i = 1 ... N) elements And, (i = 1 ... N-1) counters, (i = 1 ... N-1) multipliers, counter D, divider, adder, multiplier, trigger block, the output of which is connected to the inputs of thinning logic circuits (i = 1, 2, ..., N), the output “pass” of the first thinning logic circuit is connected to the first and second inputs of the first AND element, except Moreover, the output “transmission” (i = 2 ... N) of the throttling logic circuit is connected to the second input (i = 2 ... N) of the And element, the output of each i-th And element, except by the Nth one is connected to the first inputs of the subsequent element And, accordingly, the input of the start-up block is the information input of the device, the output of the divider is connected to the second input of the multiplier, the output of the adder is connected to the first input of the multiplier, characterized in that the Nth counter is additionally introduced into it, Nth multiplier, timer, memory unit, calculation unit Δ _k , calculation unit

calculation block

, difference block, 1 / S (n) calculation block, multiplier, logarithm block, Hurst coefficient value estimator, with the timer output connected to the input of the start block, the outputs (i = 1 ... N) of the logical circuit AND connected to the inputs ( i = 1 ... N) -th counter, the outputs "pass" of each i-th thinning logic circuit are connected to the first inputs of each i-th multiplier and the inputs of the memory block, the output of which is connected to the first input of the 1 / S (n) calculation block and the first input of Δ _k calculation unit, a second input connected to the outputs of the multipliers counters, outputs of the multipliers Uniform from the adder inputs, the output of the multiplier is connected to the second input of the calculation unit 1 / S (n) and the second input calculation block Δ _k, Δ _k output calculation unit connected to the input of calculating unit

and with the input of the calculation unit

calculation block output

connected to the first input of the difference block, the output of the calculation block

connected to the second input of the difference block, the output of which is connected to the second input of the multiplier, to the first input of which the output of the calculation unit 1 / S (n) is connected, the output of the multiplier is connected to the input of the logarithm unit, the output of which is connected to the input of the block for estimating the value of the Hurst coefficient, output unit estimates the value of the Hurst coefficient is the information output of this device, which receives the value of the estimation of the Hurst coefficient.