RU877U1 - Stereo decoder - Google Patents

Abstract

A stereo decoder containing a frequency-defining circuit, a first controllable electronic key with three switched outputs, a first phase comparison unit with two inputs, a quadrator connected by an output to the input of the first phase-locked loop, made of a series-connected phase detector, low-pass filter and generator, a frequency divider into two with two outputs and an input connected to the output of the said phase-locked loop, the first high-pass filter and the sum-difference converter, made with a four quadrant multiplier with two inputs and two outputs, to which a corrective PC filter is connected and which form the outputs of a stereo decoder, while the outputs of the frequency divider are connected by two to the corresponding two switched outputs of the first controlled electronic key, the control input of which is connected to the output the first phase comparison unit, and the third switched output of the first controlled electronic key is connected to one of the inputs of the four quadrant multiplier, the other input One of which is combined with the input of the first high-pass filter and with the first input of the first phase comparison unit, characterized in that a two-input adder, a second controlled electronic key with three switched outputs, a third, fourth and fifth controlled electronic keys with two switched outputs each, are introduced phase comparison unit with two inputs, a second high-pass filter, a second phase-locked loop made of a series-connected phase detector, a low-pass filter, a generator

Description

The utility model relates to radio engineering and can be used as a stereo sound decoder in FM broadcast receivers when receiving signals in systems with polar modulation with partially suppressed subcarrier frequency of 31.25 kHz and pilot tone frequency of 19 kHz.

A device for decoding a stereo signal in a system with a polar modulation "containing two controlled keys, a Shaper of switching pulses, two amplifiers with negative feedback, two low-pass filters and a frequency-dependent block" made on resistors and capacitor C 1 3.

The device does not provide for switching tuning frequencies and has limited application. Of the known solutions, the closest to the proposed technical essence is a stereo decoder containing a sum-difference converter with a four-quadrant multiplier and a correction RC filter, a subcarrier frequency recovery unit with a quadrator, a phase-locked loop PLL), a filter of high frequencies, frequency dividers, Phase comparison unit, frequency-defining circuit, switches and electronically controlled E Ј23 keys.

The well-known stereo decoder provides reception of broadcasting signals in systems with polar modulation with attenuation and without attenuation of the differential signal in the region of the subcarrier frequency, as well as in a system with a pilot tone, but the transition from one broadcasting system to another is carried out manually using switches, which affects its operational properties.

A device is known comprising a phase detector, a low-pass filter, frequency dividers "generator. The device is a closed circuit of automatic regulation according to the principle of phase-locked loop and provides the selection of the pilot tone frequency of 19 kHz EZZ.

The proposal is aimed at improving the performance of a stereo decoder by automatically switching from one broadcasting system to another, depending on the received signal.

This problem is solved in that in a known stereo decoder containing a frequency-setting circuit, a first controlled electronic key with three switched outputs, a first phase comparison unit with two inputs, a quadrator connected by an output to the input of the first phase-locked loop “made of series-connected phase detector, low-pass filter and generator, frequency divider into two with two outputs and

class.ZHI N O2 N 5 / OO Stereo decoder

an input connected to output} of the aforementioned Phase Frequency Lock block, the first high-pass filter and a sum-difference converter made with a four-quadrant multiplier with two inputs and two outputs that are connected to the corrective PC filter and which form the outputs of the stereo decoder, while the outputs of the frequency divider are connected to two to the corresponding two switched terminals of the first controlled electronic key, the control input of which is connected to the output of the first phase comparison unit and the third the remote output of the first electronic key is connected to one of the inputs of the four-quadrant multiplier “the other input of which is combined with the input of the first High-pass Filter and the first input of the first Fazt comparison unit, a two-input adder, a second controlled electronic key with three switched outputs, a third fourth and fifth controlled electronic keys with two switched outputs each) the second phase comparison block with two inputs, the second High-pass filter the second phase-locked loop frequency ki made of series-connected low-pass phase detector of the filter of the generator and the frequency divider into four with two outputs, one of which is connected to the other input of the phase detector; the circuit is exclusive OR connected to the outputs of the said frequency divider by four, and the output to the integrator input the inputs of the second The phase comparison unit is connected respectively to the output of the second high-pass filter and to the corresponding output of the frequency divider into four, the first input of the adder is combined with the input ohm of the second High Pass Filter and forms the stereo decoder input, the second adder input is connected to the circuit output through the third controllable electronic key. The exclusive OR output of the adder is connected to the combined inputs of the first phase comparison unit of the first High Pass Filter and the four-quadrant multiplier; the first switched output of the second controlled electronic key is connected to the output of the first high-pass filter, the second switched output of the aforementioned key is connected to the output of the integrator, and the third comm the output of the second key mentioned is connected to the quadrator input; the RC filter capacitor outputs are connected to the outputs of the fourth controlled electronic key BTbp.du f input, the first phase comparison unit is connected to the corresponding output of the frequency divider to two outputs of the frequency-setting circuit through the fifth controlled electronic key is connected to another input of the generator of the first phase locked loop in which the output of the generator is connected directly to the other input of the phase detector, and the control inputs are nnyh controlled electronic switches are connected to the output of the second comparator unit Phases.

- l stereo broadcast systems and corresponding switching of the decoder. FIG. 1 is a functional diagram of the proposed decoder “in Fig. 2, signal spectra in stereo broadcasting systems a) in a system with polar modulation with attenuation of a difference signal in the region of the subcarrier frequency, b) in a system with pilot tone, c) in a system with polar modulation without attenuation of the difference signal in the region of the subcarrier frequency

The stereo decoder contains a frequency-defining circuit 1, a first controlled electronic key 2 with three switched outputs, a first phase 3 comparison unit with two inputs, a quadrator 4 "connected by an output to the input of the first phase-locked loop 5, frequency 1 performed from a phase detector 6 connected in series, a low-pass filter 7 and generator 8, a frequency divider into two 9 with two outputs and an input connected to the output of the mentioned block 5 Phase frequency locked loop, the first FILTER high-pass Yu and total-difference conversion The 11 hour caller is made with a quadrant multiplier 12 with two inputs and two outputs, to which a correction KS-Filter 13 is connected and which form the outputs of the stereo decoder.

At the same time, the outputs of the frequency divider by two 9 are connected to the corresponding two switched outputs of the electronic key 2, the control input of which is connected to the output of the first phase comparison unit 3- The third switched output of the electronic key 2 is connected to one of the inputs of the mentioned quadrant multiplier 12 “the other input of which is combined with the input of the first High-Pass Filter 1О and with the first input of the first phase comparison block 3V stereo decoder introduced two-input adder 14, the second managed electronic key 15 with three comm with adjustable outputs, the third, fourth and fifth controllable electronic keys 16,17,18 with two switched outputs each, the second phase 19 comparison block with two inputs, the second high-pass filter 2O, the second phase-locked loop 21 made of series-connected phase detector 22, a low-pass filter 23, an oscillator 24 and a frequency divider into four 25 with two outputs, one of which is connected to the other input of the Phase detector 22, an Exclusive OR 26 circuit “connected by inputs to the outputs of the said frequency divider four 25 "and the output to the input of the integrator 27. In this case, the inputs of the Phase 19 comparison unit are connected respectively to the output of the second High Pass Filter 2O and to the corresponding output of the frequency divider by four 25

94Q / 630i

The inputs of the first phase comparison unit 3 ’of the first high-pass filter 1О and the quadrant multiplier 12 are connected together by the first ones; the first switched output of the second controlled electronic key 15 is connected to the output of the first high-pass filter 1О, the second switched output of the mentioned key 15 is connected to the integrator 27 output and the third key output 15 is connected to the input of the quadrator 4.

The terminals of the RC filter condenser 13 are connected to the terminals of the fourth controlled electronic key 17-The second input of the first phase comparison unit 3 is connected to the corresponding output of the frequency divider by two 9- The output of the frequency-setting circuit 1 through the fifth controlled electronic key 18 is connected to another input of the generator 8 of the first phase-locked loop 5, in which the output of the generator 8 is connected directly to the other input of the Phase detector 6 - The control inputs of the entered controlled electronic keys 15,16,17,18 are connected to the output of Phase 19 Comparison Unit Elements 1-9 and key 18 form a subcarrier frequency recovery unit 28, and elements 19-27 form a pilot tone recovery unit 29. In a stereo decoder, the elements of analog and digital technology are used. For example, subcarrier frequency recovery unit 28 and the sum-difference converter 11 can be performed on the basis of a type microcircuit, a phase locked loop 21 is based on a type K1561GG1 type chip, a 25-frequency divider is on a type K561TM2 type circuit, the circuit is exclusive OR 26 and the tree is comparable phase 19 - based on a type K561 / Sh2 chip; electronic keys 15-18 - on a type K561KTZ type chip R and C filters are used in the high and low pass filters; adder elements 14 are implemented on an operational amplifier, a resistor is used as a frequency-reference circuit 1 The proposed stereo decoder works as follows In the initial state, in the absence of a signal at the input of the stereo decoder, the control voltage for the output of the Phase 19 comparison unit is not supplied to the control inputs of the electronic keys, and the key 15 is in the right (according to Fng. 1 scheme) position “a to uchi 16,17,18 open The stereo input signal is fed to the first input of the adder 14 and to the input of the High-pass filter 2O in the pilot tone recovery unit 29 - 4. At the same time, the signal does not arrive at the second input of the adder 14 "and the input of the quadrator 4 is connected via cry 15 s high-pass filter outputs 10-Adder 14 in this mode is used as a repeater The work of the proposed and known decoders in this mode does not differ from each other

From the output of the adder 14, the stereo signal is fed to the input of the sum-difference converter 11 "filter 13 corrects the difference signal (A-B) Fng-2) when receiving signals with a partially suppressed sub-sub-frequency of 31.25 kHz- At the same time, the second input of the multiplier 12 is fed from the output of the block 23 recovery subcarrier frequency reference signal subcarrier frequency 31 "25 kHz.

the formation of this reference signal is as follows: from the output of the adder 14, the stereo signal is fed to the input of the High-pass Filter 10-The filtered signal is doubled in frequency by a quadrator 4 - The signal of the doubled subcarrier of 62.5 kHz is allocated by the phase-locked loop 5 then this signal is divided by frequency into two divider 9 and through an electronic key 2 enters the second input of the multiplier 12 in the form of a reference signal of a coherent subcarrier frequency of 31.25 kHz Control of key 2 is provided with the help of the unit Comparison of Phase 3 signals of the sub-carrier frequency of the input stereo signal and the reference signal coming from the corresponding output of the frequency divider 9 - When the phases of both signals coincide, the control voltage from the output of the Phase 3 comparison unit turns on the electronic switch 2 When a signal with a 19 kHz pilot signal is input to the stereo decoder, the input is also fed to the first input of the adder 14 and the input of the pilot tone recovery unit 29 — filtered by the High Pass Filter 2O, the signal is fed to the input of the PLL 21, which is extracted from the filter annogo stereo signal

19 kHz pilot tones Divider 25 operates in phase shifted mode

division so that the frequency signal is 19 kHz at the second phase input

detector 22 is shifted by -4 relative to the signal

On the first input of the pilot tone, on the other hand, at the first and second outputs of the divider 25, there are signals with a frequency of 19 kHz with a phase shift of O and - respectively. The signals from the first and second outputs of the divider 25 are fed to an exclusive OR 26 circuit at the output of which a signal is generated in the for a 38 kHz meander coherent with a 19 kHz pilot tone signal at the input of a stereo decoder-9ZG

38 kHz goes to the corresponding input of the electronic key 15.

From the first output of the divider 25, a signal with a frequency of 19 kHz arrives at one of the inputs of the Phase 19 comparison unit; the other input of which receives a filtered signal from the output of the High Pass Filter 2O. When the phases of these signals coincide, the phase comparison unit 19 generates a control voltage supplied to the control inputs of electronic keys 15-18.

In this case, the electronic key 15 is in the left position (Fig-1), and the electronic keys 16-18 are closed.

The signal from the output of the integrator 27 through the key 15 is fed to the input of the quad 4-Closure of the electronic key 16 leads to the connection to the generator 8 of an additional frequency-defining circuit 1 ensuring the operation of the stereo decoder with a subcarrier frequency of 38 kHz.

Shorting the correcting Filter 13 capacitor with an electronic key 17 provides the necessary balance of amplitudes and Phases of the total and difference signals at the outputs of the stereo decoder.

From the output of the electronic key 16, a signal with a frequency of 38 kHz is fed to the second input of the scavenger 14, at the output of which a stereo signal is formed with the spectrum shown in FigSvKvadator 4 doubles the frequency of the signal received at it.

Block 5 PLL synchronizes the operation of block 28 with a subcarrier frequency of 38 kHz The operation of the remaining blocks of the stereo decoder when receiving a signal with a pilot tone frequency of 19 kHz does not differ essentially from the work with a signal with a polar modulation with a partially-suppressed subcarrier frequency of 31.25 kHz with the only difference That their work is synchronized at a frequency of 38 kHz.

Thus, the proposed stereo decoder provides operation both in a polar modulation system with a partially suppressed subcarrier frequency of 31.25 kHz, and with a pilot frequency of 19 kHz, but unlike the known device, it implements recognition of the incoming signal and the corresponding automatic switching of the stereo decoder from one signal systems to another.

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Bibliographic data 1. Certificate of Authorship N 117O623, class MKI N O4 N 5 / OO, 1984.

2. Handbook, Sound Broadcasting, ed. Yu.A. Kovalgin, M-, Radio and Communications, p. 313.1983.

Claims (1)

A stereo decoder containing a frequency-defining circuit, a first controllable electronic key with three switched outputs, a first phase comparison unit with two inputs, a quadrator connected by an output to the input of the first phase-locked loop, made of a series-connected phase detector, low-pass filter and generator, a frequency divider into two with two outputs and an input connected to the output of the said phase-locked loop, the first high-pass filter and the sum-difference converter, made with a four quadrant multiplier with two inputs and two outputs, to which a corrective PC filter is connected and which form the outputs of a stereo decoder, while the outputs of the frequency divider are connected to two corresponding outputs of the first controlled electronic key, the control input of which is connected to the output the first phase comparison unit, and the third switched output of the first controlled electronic key is connected to one of the inputs of the four quadrant multiplier, the other input One of which is combined with the input of the first high-pass filter and with the first input of the first phase comparison unit, characterized in that a two-input adder, a second controlled electronic key with three switched outputs, a third, fourth and fifth controlled electronic keys with two switched outputs each, are introduced phase comparison unit with two inputs, a second high-pass filter, a second phase-locked loop made of a series-connected phase detector, a low-pass filter, a generator and a frequency divider into four with two outputs, one of which is connected to the other input of the phase detector, an EXCLUSIVE OR circuit connected by inputs to the outputs of the said frequency divider by four, and an output to the input of the integrator, while the inputs of the phase comparison unit are connected respectively to the output of the second high-pass filter and to the corresponding output of the frequency divider by four, the first adder input is combined with the input of the second high-pass filter and forms the input of a stereo decoder, the second adder input through the third is controlled the e-key is connected to the EXCLUSIVE OR circuit output, the adder output is connected to the combined inputs of the first phase comparison unit, the first high-pass filter and four quadrant multiplier, the first switched output of the second controlled electronic key is connected to the output of the first high-pass filter, the second to the output integrator, and the third is connected to the input of the quadrator, the terminals of the PC filter capacitor are connected to the terminals of the fourth controlled electronic key, the second input of the first comparison unit phase is connected to the corresponding output of the frequency divider by two, the output of the frequency-setting circuit through the fifth controlled electronic key is connected to another input of the generator of the first phase-locked loop, in which the output of the generator is connected directly to the other input of the phase detector, and the control inputs of the entered controlled electronic keys connected to the output of the second phase comparison unit.