RU56748U1 - DISCRETE TRANSMISSION AND RECEIVING DEVICE - Google Patents

Abstract

The utility model relates to broadband communication systems that use noise-like signals based on spreading the spectrum using a direct pseudorandom sequence. It can be land-based fixed-line systems with multiple access based on code division multiplexing. The device contains a transmitter, which includes a chip frequency generator, a carrier frequency generator, a 90 ° phase shifter, i-th (i = 1, ..., K) in-phase and quadrature channels from individual subscribers, performed identically, and each of which includes an encoder, the input of which is an input of an information signal, a first modulator, a pseudo-random sequence generator (PSP), a serial-parallel converter and a switch; a total (common) common-mode channel includes an adder and a manipulator; mmar (common) quadrature channel includes an adder, as well as a summing amplifier and antenna, and the receiver which includes an antenna, amplifier, coherent detector, carrier frequency and phase recovery unit, delay search and synchronization unit, PSP generator, as well as common mode and quadrature channels, each of which consists of a block of channel demodulators, a maximum selection block, a serial-parallel converter, a decision block of a switch, and a decoder. The technical result achieved by the implementation of the utility model is to provide high spectral efficiency, capabilities

dynamic software changes in the speed of information transfer, as well as increasing the reliability of the transmitted information. 3 ill.

Description

The present utility model relates to broadband communication systems that use noise-like signals based on spreading the spectrum using a direct pseudo-random sequence. It can be land-based fixed-line systems with multiple access based on code division multiplexing (CDMA).

The known system described in JKHolmes. Coherent Spread Spectrum System. Krieger Publishing company. Malabar Florida - 1990, p.624, using broadband noise-like signals, comprising a transmitter and a receiver. In the transmitter, the input information signal with speed served on the encoder. This encoder encodes the input bits of information into code patterns for transmission. It can be a block encoder or a convolutional encoder as described, for example, in the book by J. Clark, J. Kane, “Coding with error correction in digital communication systems.” - M. - Radio and communications. - 1987. - 391 p.

A pseudo-random sequence modulator modulates and spans the spectrum of the encoded signal from the encoder using a pseudo-random

sequence (SRP) coming from the generator SRP. A carrier frequency generator generates a signal that is modulated by a spectrally spread coded signal in a carrier frequency modulator. The resulting signal is amplified by the amplifier and emitted by the antenna.

At the receiver, the transmitted signal is received by the antenna and amplified in the amplifier. The carrier frequency and phase recovery unit restores the reference coherent signal from the received signal. With its help, a coherent detector detects a received signal and provides a detected signal to the PSP demodulator and the delay search and synchronization unit. The delay search and synchronization unit comprises an internal memory bandwidth generator that generates copies of the memory bandwidth used in the transmission bandwidth generator. The delay search and synchronization unit synchronizes between the detected signal and a copy of the bandwidth from the local bandwidth generator. These devices are described in many books, for example, A.I. Alekseev, A.G. Sheremetyev, G.I. Tuzov, B.I. Glazov "Theory and application of pseudorandom signals", publishing house Nauka, M. 1969, fig. .6.7, 6.8, 6.12 or “Noise-like signals in information transmission systems”, ed. Pestryakova V.B. M., Sov. Radio, 1973, Fig.5.5.1, Fig.5.6.2.

After establishing synchronism, the delay search and synchronization unit issues a phased copy of the SRP to the SRP demodulator. The PSP demodulator demodulates (collapses in the spectrum) the detected signal and provides

encoded signal to the decision block and decoder. The deciding unit and the decoder makes the final decision on the transmitted bits of information, collapses and decodes the channel bits into information bits output.

The closest in technical essence and the achieved effect is the spread spectrum transmission system described in US patent No. H 04 K 1/00 5414728 dated May 9, 1995 Methods and apparatus for bifurcating signal transmission over in-phase and Quadrature phase spread spectrum communication channels. "

The known system contains two information streams from users of channel 1 and channel 2, which are transmitted at a speed each in common-mode I and quadrature Q channels, respectively, or one high-speed data stream with a speed from the user by a common channel, which is first demultiplexed in the demultiplexer into two streams via each and then transmitted in-phase I and quadrature Q channels as separate users of the 1st and 2nd channels. Two information flows then go to the encoder I channel and the encoder Q channel. Coded streams arrive at time synchronization and power control blocks, where part of the coded information bits are replaced by control (service) bits. The signal of each channel is deployed over the spectrum of its individual SRP:

common-mode I channel using SRP ₁ generated by the generator SRP ₁ ; quadrature Q channel using SRP ₂ generated by the SRP ₂ generator. In PSP modulators, coded signals modulate the corresponding PSP. The spectrum-sweep data is summed with the pilot signals generated by the pilot signal generator on the I and Q channel adders. The resulting signals are then fed to the modulators of the carrier frequencies of the I channel and Q channel, respectively.

The common-mode signal generated by the I channel carrier frequency generator is phase modulated in the I channel carrier frequency modulator using the resulting signal from the I channel adder and fed to the summing amplifier. The quadrature signal received from the carrier frequency generator of channel I, followed by a 90 ° phase shift in the phase shifter, is phase-modulated in the carrier frequency modulator of Q channel using the resulting signal of the Q channel adder and fed to the summing amplifier.

After summing the I and Q signals in the summing amplifier, the resulting signal is fed to the antenna for transmission.

At the receiver, the signal is received by the antenna, amplified in the amplifier, and then processed through the I and Q channels. The carrier frequency and phase recovery unit restores the unmodulated common-mode I and quadrature Q carriers and feeds them separately to a coherent detector. In a coherent detector, the in-phase I and quadrature Q components of the received resultant signal and detected I are separately detected

and Q signals are provided at two separate outputs for further processing. Both of these signals are used in the delay search and synchronization unit to enter and maintain delay synchronism. After acquisition searcher and synchronization delay phasing generators SRP ₁ and cap ₂ so that the phase generated copies CAP CAP CAP generators ₁ and ₂ coincide with the phases of the received CAP signals. In the PSP demodulator there are two separate demodulators for in-phase I and quadrature Q signals, to which separately copies of the PSP from the generators of the PSP ₁ and PSP _2, respectively, are supplied. As a result of demodulation (convolution of signals over the spectrum), the detected signals without spreading the spectrum come from the output of the demodulator, which are further processed in the decoder and multiplexer.

In the nearest analogue under consideration, two orthogonal pseudo-random sequences (PSP) are allocated to each subscriber station. One SRP is used for direct spectral expansion in the in-phase channel, the other SRP is used for direct spectral expansion in the quadrature channel. Then, both components of the signal — in-phase and quadrature — are added up in a summing amplifier and are emitted by a transmitter at one carrier frequency in the direction of the receiver (central station receiver). With this method of transmission, the emitted signal is obtained at a constant level (the envelope peak factor is unity), which allows the use of low-cost transmitters operating in a nonlinear mode.

The disadvantages of the system described in patent 5414728 are:

- deterioration in the reliability of the transmitted information due to the replacement of part of the information bits with control (service) bits;

- as pilot signals for each user, copies of a pseudo-noise sequence of length 2 ¹⁵ shifted relative to each other are used, as a result of which the pilot signals from different subscriber stations at the input of the central station are not orthogonal to each other;

- low spectral efficiency γ

If B is the information transfer rate for each (in-phase and quadrature) information channel, then the maximum allowable input transmission rate of the subscriber station is 2V. If it is necessary to transmit two, three, five times faster speed, two, three, five subscriber stations must be switched on. This solution is not economical. The spectral efficiency of this system is

where 2B is the input transmission rate of the subscriber station;

ΔF - occupied bandwidth;

M is the number of subscriber stations operating in the same frequency band at the same time by the method of multiple access with code division multiplexing (CDMA).

With direct expansion of the spectrum, the base n of the SRP is approximately equal to

taking into account that the chip frequency f _{ch is} approximately equal to f _ch ≈ΔF. For each subscriber station, two SRPs must be allocated.

Therefore, the number of simultaneously operating stations M is

taking into account that the total number of orthogonal SRP is equal to the base of n signals.

Substituting (3) into (1) we finally obtain

So, the spectral efficiency of the closest analogue is not maximum (γ = 1 <2, where the value “2” corresponds to the maximum achievable spectral efficiency with QPSK modulation, which is used both in patent 5414728 and in the proposed utility model) and the input data rate is limited size . The purpose of this utility model is to create a system for transmitting discrete information with a higher spectral efficiency (γ> 1). To achieve this technical result, it is proposed at each subscriber station to modulate both by inverting the PSP phase and by selecting one of the PSP from the total number N, where

The problem is solved in such a way that in the central and subscriber stations of the system for transmitting and receiving discrete information using wideband noise-like signals in the code division of channels containing the i-th (i = 1, ..., K) in-phase and quadrature channels from of individual subscribers, performed identically, and each of which includes an encoder, the input of which is an input of an information signal, the first modulators, a pseudo-random sequence generator (PSP), in the composition of the total (common) sinf The adder and manipulator are included in the channel, and the adder as well as the carrier frequency generator, the output of which is connected to the other input of the second modulator of the total (common) common mode channel and through the phase shifter, to the other input of the second sum modulator, is part of the total (common) quadrature channel the common) quadrature channel, and the outputs of the second modulators of the total (common) common-mode and quadrature channels through the summing amplifier are connected to the antenna, and in the receiver, the antenna, amplifier, and An inert detector, as well as in-phase and quadrature channels, each of which includes a decision block and a demodulator, and the outputs of the coherent detector are connected respectively to one of the inputs of the demodulators of the in-phase and quadrature channels, as well as the PSP generator, a chip frequency generator is introduced into the transmitter, and a serial-parallel converter and a switch are respectively introduced into the in-phase and quadrature channels, and in the in-phase and quadrature channels, the encoder output is connected to the input flax parallel

a converter whose “K” outputs are connected to the corresponding control inputs of the switch, the output of which and the (k + 1) serial-parallel converter output are connected to the corresponding inputs of the first modulator, and the “N” outputs of the PSP generator are connected to the corresponding inputs of the in-phase and quadrature channel switches and the output of the chip frequency generator is connected to the clock input of the PSP generator, the control outputs of which are connected to the corresponding readout inputs of the series-parallel converters the inphase and quadrature channels, and a carrier frequency recovery block and a delay search and synchronization block are introduced into the receiver, and a maximum selection block and series-connected switch, a parallel-serial converter and a decoder, and in-phase and quadrature channels are made in the form of N-channel demodulators, while the N outputs of the PSP generator are connected to the corresponding inputs of the N-channel demodulators quadrature channels, in each of which N outputs of the N-channel demodulator are connected to the corresponding inputs of the decision block and the maximum selection block, “k” of the outputs of which are connected to the corresponding inputs of the parallel-serial converter and to the control inputs of the switch, to the inputs of which the corresponding outputs of the decision the block, the outputs of the carrier frequency recovery block are connected to the corresponding inputs of the coherent detector, the input and the control input

The carrier frequency recovery unit is connected respectively to the output of the amplifier and to one of the control outputs of the PSP generator, the other control outputs and the control input of which are connected to the corresponding inputs and the output of the delay search and synchronization unit, the outputs of which are connected respectively to the control inputs of parallel-in-phase converters and quadrature channels, to the control inputs of the decision block and the block for selecting the maximum in-phase channel and to the control inputs of the decision block Single and quadrature channel selection unit maximum.

The invention is illustrated in figures 1 and 2, which shows the proposed device for transmitting and receiving discrete information.

Figure 1 shows the structural functional block diagram of the i-th in-phase and quadrature channels of the transmitter, figure 2 presents the functional block diagram of the total (common) in-phase and quadrature channels of the transmitter, and figure 3 is a functional block diagram of the receiver.

The i-th transmitting channel of the transmitter (Fig. 1) includes two identical channels - in-phase and quadrature channels, made identically, which include encoders 1 and 2, a chip frequency generator (HF) 3, serial-parallel converters 4 and 5 , the first modulators 6 and 7, the switches 8 and 9, the pseudo-random sequence generator (PSP) 10. The total (common) in-phase and quadrature channels of the transmitter (Fig. 2) include adders 11 and 12,

manipulator 13, second modulators 14 and 15, carrier frequency (LF) generator 16, 90 ° phase shifter 17, summing amplifier 18 and antenna 19. The receiver (Fig. 3) includes antenna 20, amplifier 21, coherent detector 22, in-phase and quadrature channels, which include N-channel demodulators 23 and 24, decision blocks 25 and 26, switches 27 and 28, parallel-serial converters 29 and 30, maximum selection blocks 31 and 32, carrier recovery unit (HV) 33, PSP generator 34, delay search and synchronization block 35, decoders 36 and 37.

A device for transmitting and receiving discrete information operate as follows.

As shown in figure 1, information data can be received at the inputs of encoders 1 and 2 from two independent sources of information or from one high-speed source through a demultiplexer, at the output of which the speed of the information stream is reduced by 2 times. After coding in encoders 1 and 2, the information then goes to series-parallel converters 4 and 5, is parallelized to (k + 1) outputs, as a result of which the speed at each output decreases (k + 1) times. The signals from the "k" outputs of the serial-parallel converters 4 and 5 are fed to the control inputs of the switches 8 and 9. Depending on the type of "k" binary information symbols on the control inputs of the switches 8 and 9 at the outputs of these switches, one of N = 2 ^k SRP from the generator SRP 10. The signal from the output (k + 1) of series-parallel converters 4 and 5 is fed to one of the inputs of the first

modulators 6 and 7, in which it undergoes pseudo-random modulation using one of the SRP selected using switches 8 or 9. The PM 3 generator controls the PSP 10 generator, the control outputs of which are connected to the reading inputs of the serial-parallel converters 4 and 5, which ensures their synchronization, due to which the beginning and end of each selected PSP coincides with the beginning and end of each bit of information. With the outputs of the first modulators 6 and 7, streams of data i-th in-phase and quadrature channels S _Ii and S _Qi are deployed over the spectrum of data, respectively.

As shown in Fig. 2, the streams of the common-mode channels S _{Ii, which} are unfolded over the data spectrum, are fed to the N inputs of the adder 11. At the (N + 1) -th input of the adder 11, the pilot PSS R received from the (2 ^k +1) PSP generator 10 and supplied to the manipulator 13, to the other input of which control (service) bits C are received and which replaces a part of the pilot PSP bits with control (service) bits. The streams of quadrature channels S _Qi unfolded over the data spectrum are fed to the N inputs of the adder 12. The outputs of the adders 11 and 12 are connected to the inputs of the second modulators 14 and 15, the second inputs of which receive a signal from the output of the LF generator 16 directly and through the phase shifter by 90 ° 17. From the outputs of the second modulators 14 and 15, the signals through the summing amplifier 18 are emitted by the antenna 19.

By reducing the speed in converters 4 and 5, it is possible to transmit high-speed information with a large base bandwidth.

By changing the number of used memory bandwidths at a given station, one can change the transmission speed without changing the base n, the chip frequency, the occupied bandwidth, which allows multi-speed modems to be made without changing the parameters of the radio path of the transmitter and receiver.

In order not to clutter the structural block diagram of the receiver, in Fig. 3 only one of the plurality of receiving channels is displayed, intended for processing a pair of information signals. In the receiver, the signal from the antenna 20 after amplification in the amplifier 21 is fed to the coherent detector 22 and the carrier frequency and phase recovery unit 33. After the coherent carrier and coherent detection of the in-phase and quadrature components are isolated, the video signals of these components are fed to the N-channel demodulators 23 and 24 of the in-phase and quadrature channels and at the same time to the search and synchronization block by delay 35, which, after entering synchronism, phase generator 34 and the operation of decision blocks 25 and 26, maximum selection blocks 31, 32 and p are parallel-to-serial converters 29 and 30. N-channel demodulators 23 and 24 have individual demodulators SAPs in an amount of N = 2 ^k for each of the possible memory bandwidth used for transmission. Therefore, on one of the individual demodulators of the SRP, the signal will be convolved along the spectrum, and on all other (2 ^k -1) individual demodulators of the SRP

the convolution result will be zero. The maximum selection blocks 31 and 32 determine, according to the maximum energy, the individual demodulator of the memory bandwidth on which the convolution took place, and output k bits of information to parallel-serial converters 29 and 30 for converting them into serial code and k bits of information to the switches 27 and 28 for issuing solutions from decision blocks 25 and 26, which correspond to individual demodulators of the memory bandwidth on which the convolution has occurred. One bit of information from the output of the switches 27 and 28 and k bits from the output of the maximum selection blocks 31 and 32 are converted into parallel-serial converters 29 and 30 into a serial code with a data rate increase (k + 1) times and are output to decoders 36 and 37 and then to two recipients separately or after multiplexing in the multiplexer to one recipient with an increased data rate.

Depending on what bandwidth was used for transmitting the received information bits, the convolution will be carried out in one of the subchannels of the N-channel demodulator, each of the subchannels of which contains an integrator for the duration of one bit. Next, the convoluted signal is supplied to a decision block, which contains a decision device for each of the N subchannels.

The decider of its subchannel determines the sign of the transmitted bit ("+" or "-", ie 0 or 1). At the same time, the convoluted signal from the N-channel demodulator enters the maximum selection block. The maximum selection block determines the maximum of the voltages at the outputs of N integrators and

it determines which of the N memory bandwidths was used for this particular set of k bits of information. On the one hand, the maximum selection block through the switch opens the way to the output of the N-channel decision block, in the subchannel of which the highest convolution result is observed. On the other hand, the same block also gives a decision on the set of k bits of information by which one SRP from N was selected for transmission. After that, k bits of information from the output of the maximum selection block and one bit from the output of the switch are converted in the parallel-serial converter into the output stream of the in-phase or quadrature channel, decoded in the decoders 36 and 37 of both channels and output at a speed of b / s or additionally multiplexed into multiplexer into the stream at a speed of 2V b / s.

In the proposed utility model, the base (length) n of the SRP is defined as

The maximum number of stations M with a predetermined number N = 2 ^k SRP plus one pilot SRP for each station is

Spectral efficiency - γ of the entire system of M stations is

In the proposed utility model k = 1, namely: two information bits are modulated by one memory bandwidth. Therefore, the spectral efficiency of the system is γ = 1.33, which is higher than in the closest analogue.

Thus, the proposed device transmission and reception has a higher spectral efficiency compared with the closest analogue.

The system allows the simultaneous operation of several stations with different information transfer rates.

A big advantage of the proposed device is the ability to program the stations according to requests for different operating speeds by centralizing the distribution of the common bandwidth resource between subscribers. It is also an advantage that one of the set of SRP is used as a pilot signal; therefore, the pilot signals from many subscriber stations at the input of the central station are orthogonal to each other. And, due to the fact that the control (service) bits are transmitted inside the pilot signal, the reliability of the data transmitted by the user is increased.

The utility model can be implemented on the appropriate elemental base for standard technologies.

Using the utility model will allow for the provision of all types of broadband services, starting with ADICM 32 kb / s, PCM 64 kb / s, 2B + D = 144-192 kb / s, conference calling 384 kb / s, Internet access 512, 1024, 2048 kb / s with a constant base bandwidth, a constant chip frequency,

constant bandwidth of the used signals without changing the parameters of the transmitter and receiver.

Information sources:

1. J.K. Holmes "Coherent Spread Spectrum System", Krieger Publishing company, Malabar, Florida, 1990, p. 624.

2. J. Clark, J. Kane "Coding with error correction in digital communication systems", M .: Radio and communications, 1987, 391 pp.

3. A.I. Alekseev, A.G. Sheremetyev, G.I. Tuzov, B.I. Glazov "Theory and application of pseudorandom signals", Moscow: Nauka, 1969, Fig. 6.7, 6.8, 6.12.

4. “Noise-like signals in information transmission systems,” ed. Pestryakova V.B., M., Sov. Radio, 1973, fig. 5.5.1, fig. 5.6.2.

5. US patent No. 5414728, N 04 K 1/00 dated May 9, 1995 "Methods and apparatus for bifurcating signal transmission over in-phase and Quadrature phase spread spectrum communication channels". - prototype

Claims (1)

A device for transmitting and receiving discrete information, which contains the i-e (i = 1, ..., K) in-phase and quadrature channels from individual subscribers, performed identically, and each of which includes an encoder, the input of which is an input of an information signal , the first modulators, a pseudorandom sequence generator (PSP), the total (common) common-mode channel includes an adder and a manipulator, and the total (general) quadrature channel includes an adder and a carrier frequency generator, the output of which is connected with another input of the second modulator of the total (common) common-mode channel and through a phase shifter - with another input of the second modulator of the total (common) quadrature channel, and the outputs of the second modulators of the total (common) common-mode and quadrature channels are connected to the antenna through a summing amplifier, and in the receiver a series-connected antenna, amplifier and coherent detector, as well as in-phase and quadrature channels, each of which includes a demodulator and a decision unit, and the outputs of the coherent detector are connected respectively, with one of the inputs of the demodulators of the in-phase and quadrature channels, as well as the PSP generator, characterized in that the chip frequency generator is introduced into the transmitter, the serial-parallel converter and switch are respectively introduced into the in-phase and quadrature channels, and the output in common-mode and quadrature channels the encoder is connected to the input of the serial-parallel converter, k outputs of which are connected to the corresponding control inputs of the switch, the output of which and (k + 1) the output through an ice-parallel converter is connected to the corresponding inputs of the first modulator, N outputs of the PSP generator are connected to the corresponding inputs of the in-phase and quadrature channel switches, the output of the chip frequency generator is connected to the clock input of the PSP generator, the control outputs of which are connected to the corresponding reading inputs of the serial-parallel in-phase and quadrature channels, one of the set of memory bandwidth is used as a pilot signal, and control (service) bits are transmitted inside the pilot signal, the carrier frequency recovery unit and the delay search and synchronization unit are introduced into the receiver, the maximum selection unit and the series-connected switch, the parallel-serial converter and decoder, the common-mode and quadrature channel demodulators are implemented in the common-mode and quadrature channels in the form of N-channel demodulators, while the N outputs of the SRP generator are connected to the corresponding inputs of the N-channel demodulators in-phase and quadrature channel each of which N outputs of the N-channel demodulator are connected to the corresponding inputs of the decision block and the maximum selection block, k outputs of which are connected to the corresponding inputs of the parallel-serial converter and to the control inputs of the switch, to the inputs of which the corresponding outputs of the decision block are connected, the outputs the carrier frequency recovery unit is connected to the corresponding inputs of the coherent detector, the input and control input of the carrier frequency recovery unit are connected respectively to the output of the amplifier and one of the control outputs of the PSP generator, the other control outputs and the control input of which are connected to the corresponding inputs and the output of the delay search and synchronization unit, the outputs of which are connected respectively to the control inputs of parallel-serial converters in-phase and quadrature channels, to the control inputs a decision block and a block for selecting a maximum of the in-phase channel to the control inputs of a decision block and a block for choosing a maximum of a quadrature channel.