RU5272U1 - MULTI-PROCESSOR SYSTEM - Google Patents

Abstract

A multiprocessor comprising first-level processor elements interconnected by a direct hypercube binary network, characterized in that a second-level processor element, two redundant first-level processor elements and an information bus are additionally introduced, while the second-level processor element is connected to each processor element of the first level two-way communication via the information bus, redundant processor elements of the first level are connected to the rest of the processor E-layer network elements of the first direct links, but with the second level processing element - via the data bus.

Description

Multiprocess system

The well-known modep belongs to the compounds of the deductible equipment and is intended for solving complex scientific and technical problems. The multiprocessor system (hereinafter referred to as the multiprocessor) is an independent device and is integrated with a control computer of type RS / YT, which implements the FUNCTIONS of control and interaction of the multiprocessor with an external computing environment.

Similar foreign multiprocessors are known: eight processor versions of the iPSC 860 Intel FIRM (USA), NCube / Ten screens NCube (SSR1), Butterfly Plus screens BBN Advanced Computers / 1 /. They consist of eight processor elements connected by a network of direct connections according to the binary hypercube scheme. The disadvantage of these multiprocessors is the lack of hardware support | ryzhki group exchanges, which does not allow to fully support the effective interaction of processor elements. The eight-processor version of the multiprocessor / 1 / is the closest in technical essence to the described model. This multiprocessor consists of eight processor elements connected by a network of direct connections according to the binary hypercube scheme. In this case, I / O modules can be connected to the network of direct connections, through which communication with the external computing environment is carried out.

The disadvantage of the prototype is that the lack of hardware support for group exchanges reduces the effectiveness of the interaction of the processor elements, and the failure of one of the processor elements leads to a failure or a sharp decrease in the performance of the whole multiprocessor as a whole.

The technical problem to be solved consists in increasing system performance (reducing the times of 1 counting of parallel tasks) and the reliability characteristics of the multiprocessor.

The task. is solved as follows. A multiprocessor containing first-level processor elements interconnected by a network of direct connections according to the binary hypercube scheme additionally introduces a second-level processor element, two redundant processor elements of the first LEVEL and an information bus, while the second processor element

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V /.

IPC G 06/15/80

the level is connected to each processor element of the first level by two-way communication via the information bus, the backup processor elements of the first level are connected to the remaining processor elements of the first level by a direct communication network, and to the processor element of the second level through the information bus.

Distinctive features of the prototype are the following features: a second-level processor element, two redundant first-level processor elements and an information bus are additionally introduced into the multiprocessor, while the second-level processor element is connected to each first-level processor element by two-way communication via the information bus, redundant processor elements of the first level connected to the rest of the processor elements of the first level by a network of direct connections, and with the processor element of the SECOND equal through the information bus.

The specified set of features allows you to expand the computing capabilities of the PC in solving scientific and technical problems, due to the possibility of dividing the tasks into several parallel subtasks and their autonomous solution on the processor elements of the first level, and the solved subtasks are then quickly collected on the processor element of the second level and the finished result is issued in PC. When using redundant processor elements of the first level significantly increases the reliability of the multiprocessor.

The utility model is illustrated by the following figures: FIG. 1 shows a block diagram of a multiprocessor.

The multiprocessor (Fig. 1) contains processor elements of the first level (1), interconnected by a network of direct connections (2) according to the binary hypercube scheme.In addition, a processor element of the second level (3), two backup processor elements of the first level (4) and information bus (5), while the processor element of the second level (3) is connected to each processor element of the first level () by two-way communication via the information bus (5), the redundant processor elements of the first level (4) are connected. with the rest of the pr mi elements of the first level (1) direct network links (2) and on the second level processing element (3) through an information SHI1-SU (5).

The multiprocessor contains processor elements of the first level, implemented on a high-performance RISC microprocessor i860 FIRM Intel Corporation USA / 1 /. The processing elements of the first level are counting elements, on which an autonomous solution of the parts of the problem takes place, and are interconnected by a network of direct connections according to the binary cube scheme / 2 /. A second-level processor element is introduced into the multiprocessor structure, which is connected to each first-level processor element by two-way communication via the information bus and is designed to transmit the counting results to a PC. It can also be used to count consecutive task fragments and communicate with external devices. The multiprocessor contains redundant processor elements of the first level, which are connected to the remaining processor elements of the first level through a network of direct connections, and to the processor element of the SECOND level through the information bus.

The multiprocessor operates as follows.

Programs and data from the PC enter the second-level processor element (3), which sends them via the information bus (5) to the first-level processor elements (1). After that, the processor elements of the first level (1) make parallel execution of the program, exchanging, therefore, the intermediate results of the account through a network of direct connections (2) with each other. Exchanges are carried out either asynchronously between any two processor elements of the first level (1), or SYNCHRONOUSLY under the control of a processor element of the second level (3) between a group of processor elements of the first level. At the end of the program, the processor elements of the first level (1) provide the results of calculations through the information bus (5) to the processor element of the second level (3) and, further, to the PC.

In case of failure of any of the processor elements of the first level (1), after software reconfiguration, its FUNCTIONS will be performed by one of the backup processor elements (4).

A prototype of a multiprocessor based on a 64-bit RISC microprocessor with a clock frequency of 33 and 40 MHz, a peak performance of 640 MFLOPS (with single precision) and 480 MFLOPS (with DOUBLE precision), with a total memory capacity of 16 to 256 MB, and system bandwidth was manufactured interprocessor exchange of at least 300 MB / s, bandwidth

Sources of information taken into account when filling out the application:

1.i860 64-8IT MICROPROCESSOR HARDWARE REFERENCE MANUAL, INTEL Corporation, 1989, Order Number: 240330-002.

2.SPECIFICS iPSC-860, INTEL Corporation, 1990 (analogs and prototype).

Claims (1)

A multiprocessor comprising first-level processor elements interconnected by a direct hypercube binary network, characterized in that a second-level processor element, two redundant first-level processor elements and an information bus are additionally introduced, while the second-level processor element is connected to each processor element of the first level two-way communication via the information bus, redundant processor elements of the first level are connected to the rest of the processor E-layer network elements of the first direct links, but with the second level processing element - via the data bus.