RU42724U1 - HARDWARE IP telephony gateway platform - Google Patents

Abstract

The solution relates to communication technology. A hardware platform for IP-telephony gateways is proposed, which contains a central processing unit (CPU), programmable read-only memory (ROM), random access memory (RAM), liquid crystal display (LCD), programmable multi-channel packet switch (PMP), digital signal processor (DSP) ), digital-to-analog and analog-to-digital converters (DAC / ADC), telephone line controllers, Ethernet LAN controller, data ports, address tin, data bus, control bus. A hardware version of the IP-telephony gateway platform is proposed, which provides the simultaneous operation of a large number of telephone communication channels, eliminates the effect of communication channel multiplication on software, and changes the composition of the element base.

Description

The solution relates to communication technology.

As a prototype, a typical modern hardware platform for the IP68 telephony gateway MC68EZ328 of Motorola was selected, which is described in detail on the Internet site: http://e-www.motorola.com/webapp/sps/site/prod_summaru. jsp? code = MC68EZ328 & node Id = 018rH3vL2v in the "Product Brief MC68EZ328 - Dragon Boll-EZ Integrated Portable System Processor" section.

The IP telephony gateway hardware platform contains a central processing unit (CPU), programmable read-only memory (ROM), random access memory (RAM), liquid crystal display (LCD), digital signal processor (DSP), digital-to-analog and analog-to-digital converters (DACs) / ADC), telephone line controllers (KTL). Ethernet LAN controller, data ports, address bus, data bus, control bus.

Transmission ports via the data bus are connected directly to the input of the central processing unit (CPU).

The disadvantages of the known solution: the inability to simultaneously process a large number of communication channels transmitting voice data packets, due to the limited power and software of the central processing unit (CPU); the increase in communication channels requires a change in software tools embedded in the CPU.

These shortcomings are addressed by the proposed solution.

The task at hand is the improvement of the hardware platform of IP-telephony gateways.

The technical result is an expansion of functionality, an increase in the number of telephone communication channels, a change in the composition of the element base.

This technical result is achieved by the fact that in the hardware platform of the IP-telephony gateways containing a central processing unit (CPU), programmable read-only memory (ROM), random access memory (RAM), liquid crystal indicator (LCD), digital signal processor ( DSP), digital-to-analog and analog-to-digital converters (DAC / ADC), telephone line controllers (KTL) Ethernet LAN controller, data ports, address bus, data bus, control bus. a new unit has been introduced - a programmable multi-channel packet data switch (PMP) block, connected between the CPU and the DSP, the input of which is connected., data ports, and the output of the programmable multi-channel data packet switch is connected via the data bus to the central processing unit (CPU), output The CPU through the control bus is connected to one of the inputs PPMP.

Functional diagram of the proposed hardware platform of the IP-telephony gateways is shown in the drawing of Figure 1; functional diagram of the prototype shown in figure 2.

Functional diagram of a multi-channel gateway is shown in figure 1. It includes a central processing unit 1, software read-only memory 2, random access memory 3, liquid crystal display 4, programmable multi-channel packet selector 5. digital signal processor 6, digital-to-analog 7 and analog-to-digital 8 converters, controllers 9 telephone lines, controller 10 local Ethernet networks, data transfer ports 10, address bus 11, data bus 12 and control bus 13. A programmable multi-channel packet switch 5 is connected between the central a processor device 1 and a digital signal processor 6. Data ports 10 act on the inputs of the switch 5, the output of the switch 5 is connected to the central processor device via the data bus, and the output of the central processor device 1 through the control bus 13 is connected to one of the inputs of the switch 5 ..

A feature of the gateway is that all the operations of the interaction of the CPU with the data lines of voice packets are implemented through a specialized programmable, for example, eight-channel packet switch (PMPP). The power of the CPU, the software and the underlying architecture remain unchanged, the same as in the case of the original multi-channel hardware platform - the prototype shown in Figure 1.

Thus, the introduction of a new element, a programmable multi-channel data switch allows, firstly, to improve the technical performance of the platform: unloads the CPU, combining its work with the standard number of telephone ports from 1 to 8; allows you to switch to a new structural diagram with an additional function - scaling, which does not affect the software. Secondly, minimize the cost of the platform.

The hardware platform works according to the following stagewise scenario.

1. When the handset is picked up on any (or several) telephone set connected to RJ-7, KTL 9 captures this action and notifies CPU 1 through PMPP 5 ..

2. The program embedded in the EPROM 2 uses the CPU 1 to send a command to the CTL 9 to turn on the tone of the beep and put the DSP 6 in the mode of determining the set of tones of the telephone keypad.

3. DSP 6 notifies CPU 1 of the set of tones corresponding to each successively pressed key of the dial number.

4. When the dialing is completed, the CPU 1 program uses KLS 10 to communicate via the IP network with another gateway or IP phone corresponding to the requested number.

5. Through the IP network, signaling information is exchanged between the gateways. The exchange includes the coordination of compression algorithms or voice coding, information about the availability of the subscriber, call forwarding, etc.

6. The program embedded in CPU 1 includes the generation of long beeps on KTL 9, which are heard in the handset of a telephone connected to RJ-7.

7. The gateway of the called subscriber sends a signal on the IP_ network that the receiver is off-hook. In response, the CPU 1 program disables the long beeps of the call to KTL 9, and then turns on the sound recording and playback mode with previously established compression algorithms.

8. The voice signal from the microphone of the telephone (RJ-7) goes to the ADC 8 and is converted to digital form in the A-Law format. The DSP receives a continuous stream of digitized sound and encodes it, compressing it in packets of 20 milliseconds. Each packet is transmitted using CPU 1, where the program adds to the packet the information necessary for forwarding over the IP network, and then transfers the packet to the CLS. 10. After CLS 10, the packet is sent over the network to the called party, in the gateway of which these packets are unpacked and played.

9. Similarly, voice packets coming from the subscriber fall into the CPU 1 from the CLS. 10. The CPU 1 program sends them to the DSP 6, where they are unpacked one after

to others, and in the form of a continuous stream in A-Low format, they are fed to the DAC, where they are converted into an analog voice signal from a tube connected to RJ-7.

Based on a hardware platform with a CPU switch, a new series of IP-telephony gateways has been created with the number of telephone ports from 1 to 8.

In conclusion, we note that one of the options for the platform presented in Figure 2 was experimentally implemented and confirmed its new properties noted above.

Claims (1)

An IP telephony gateway hardware platform containing a central processing unit, software read-only memory, random access memory, liquid crystal display, digital signal processor, digital-to-analog and analog-to-digital converters, telephone line controllers, Ethernet LAN controller, data ports, address bus, data bus and control bus, characterized in that a program is connected between the central processing unit and the digital signal processor ble multichannel data packets switch, which is connected to the input data ports, and its output is connected to the central processing unit via a data bus, the output of the central processing unit via a control bus connected to one of the switch inputs.